LDO Noise rejection

I see then and now, *NO* comment about 5 volts (except from you).

You missed it then. It was only the 5th post in the thread. You missed it because the OP must not be very familiar with newsgroups and added his comment to the end of a signature.

Look again. 10/2 2:21 PM Others all through the thread talk about working with the cap charging to 9 volts then dropping to 5.

All three terminals "free" ??

I think I know where your coming from now.

An assumption is that the fab process allows multiple minimum size transistors in the same collector region. Placing multiple complete transistors will certainly eat up a lot of space. Noting that making one large emitter bipolar will result in dreadful beta. I am talking high current here, not where a minimum size mos is smaller than a minimum size bipolar because min is different for each.

Note that the gm of a bipolar is at least 4 X a mosfet, irrespective of the W/L of the mosfet. A shift of 120mv to go from say, 0.7 to 0.82 for a 1ma to

Kevin Aylward

It is not intended to reduce early effect, it is used to eliminate base current error. For example, if the mirror ratio was say 10:1, even with a beta of 100, the error is going to be 20%.

Draw a mirror. Disconnect the collector base short. Connect collector to gate of nmos, connect source of nmos to base.

Kevin Aylward

Exactly.

The caveat is that the nmos must be sized right. If the base current is very small and/or the mosfet is too strong, there can be problems in the nmos not turning off over process corners. It helps to put some extra bleed current into the nmos.

Kevin Aylward

OK, you didn't mention the mirror ratio before, so I had problems trying to figure out what you were doing.

OK, standard source follower. Probably a plain emitter follower would also work as a sort of Darlington with the collector grounded.

Just tried it. Seems to work fine. Gives slightly higher gain than the nmos or the plain current source.

Presumably it could use the same transistor type as the plain current source, and it should not require any extra process steps. Depending on the nmos threshold, it might also offer slightly lower voltage drop - important in low voltage applications.

With a higher gm in the bipolar, the noise should also be lower.

The zero offset voltage is nice, though--it saves a diode drop, eliminates beta error completely, and doesn't increase the noise.

Local feedback wins again!

Cheers

Phil Hobbs

But it's not zero volts offset unless the loading current is _exactly_ IDSS.

In a chip, where device count is a secondary consideration, I'm sure I can devise a scheme to compensate everything to get it to zero, or very close. ...Jim Thompson

Sure thing. Another matched FET from the bases to the emitters would be a start, and of course you can always build in an op amp to zero out the offset. ;) (Of course that would get rid of most of the noise benefit, since it wouldn't be the BJT's gain that was dominating the loop.

Cheers

Phil Hobbs

These aren't the most sterling of devices... you'd need to match VDS as well if you were really squeezing mV's. ...Jim Thompson

On Mon, 06 Oct 2014 13:12:46 -0700, Jim Thompson Gave us:

Look at the descriminator circuits on GPS receivers. They grab some of the smallest signals ever... right down next to the noise floor.

actually once the spread sprectrum spreading is undone i.e. the signal is unspread, the BW is only about 10 Hz and the SNR is pretty high.

Mark

Of course they do.

(I designed the analog portions of the very first Garmin GPS receiver chip >:-)

But what does that have to do with matching current mirrors ?? ...Jim Thompson

Just a thought.

I'm presuming efficiency is not important, or you would be using a switcher or some other external means of regulation.

If you want good supply rejection, what is wrong with having a P-channel mirror. The transistors can be sized to provide a 10:1 or more current gain. Then amplifier gain becomes earth referenced, rather than PS input referenced, if you see what I mean. Stability may still be an issue.

Is the 5V to be made available for external decoupling?

BTW - I corrected the 9V to 5V

Yes pseudo Darlington works typically, but a key point of the 0Vt device version is that it works at a much lower supply voltage.

The natural/native Vt is before the processing that moves it up!

Typically, further processing will move the natural nmos up to 0.7V vt and the natual pmos down from, say, 1.5V to 0.7V.

It saves a whacking 0.7V. Designing at 0.18u and 1.8V is where the technique works wonders.

For LDOs, it is also great as a source follower buffer from the high impedance gain stage driving the large capacitance pmos output device, to achieve faster response.

A standard Vt pmos source follower will cause significant loss of on voltage to the output device. A standard nmos follower, will not allow the output pmos to be turned fully off on light loads. Example is 2.7V in to

Kevin Aylward

Tanks? Where? Are they coming already?

Because most have no comp pin piped out and on some of them the datasheet is bordering on a flat-out lie.

I got into LDO designs just like I do everything else...

A client's president once said that the best and most fun projects are those where, after your customer signs on the dotted line, you first develop a serious knot in the stomach.

OTOH, those chips don't go *PHUT* as easily the millisecond Vladimir goes ballistic and triggers a big one :-)

Coming soon to your local police department.

I'm not talking off-the-shelf... rolling your own chip allows some proprietary advantage >:-}

Yep ;-) I have learned so many design techniques by claiming expertise yet to be obtained. The funny thing is that often I do end up becoming the expert because I have no preconceptions of how to attack the problem... so my "outside-the-box" solutions turn out to be the best solution.

The modern multi-voltage processes from X-Fab are marvelous. ...Jim Thompson

Those are good applications, but they are a bit outside the original topic of current mirrors. If you can add 0Vt devices to the process, and the current requirement is low, why not make the entire current mirror from cmos? For example, see the Typical Applications section starting on page 10 of

ALD claims entire circuits can be made to function on as little as 0.2V:

Sorry, starts on page 9.