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dealing with NGO files

I'm trying to integrate a piece of IP that was delivered in NGO format into a verilog design. I've scoured the ISE and XST documentation and the Xilinx answers database and there is really not a complete description of this flow. I'm assuming the IP provider sythesized the block to EDIF (with Synplify I think), then used edif2ngd to convert the EDIF netlist to NGO. This block is being provided for free by a Japanese company as part of a convoluted foundry relationship and I have no recourse for help from them.

I can place and route the NGO file by itself, but I can't get XST to run with the NGO module instantiated in the verilog. I've tried the

// synthesis attribute box_type of IP_BLOCK is "black_box";

synth directive but XST seems to ignore it. If I try to add the NGO file to the ISE project the file gets added as a top-level module instead of down in the hierarchy where it belongs, and the instantiated block remains unkown to ISE. When I run XST it immediately gags because it can't find the block (despite the black_box directive). I've also tried inluding a verilog description of the port list for the block in the project, which ISE recognizes and then the instantiated block is no longer unkown, but when I run XST I get some bizarre errors.

Basically I'm flailing here. Any help appreciated.

Bob S.

Reply to
RobJ
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Should work Ok; XST doesn't need to know anything about your module apart from it's I/F.

How are you declaring the module in your Verilog code? What error messages are you getting?

Reply to
Evan Lavelle

Hi Evan -

Here how the NGO module is instantiated:

ip_block ip_block_inst( .port0(port0_wire), .port1(port1_wire) ); // synthesis attribute box_type of ip_block is "black_box";

When I instantiate the ip_block verilog interface in ISE instead of the NGO file, here is what I get:

=========================================================================

  • HDL Compilation * ========================================================================= Compiling source file "../src/ip_block.v" Module compiled Compiling source file "../src/ip_block_wrapper.v" Module compiled No errors in compilation Analysis of file succeeded.

=========================================================================

  • HDL Analysis * ========================================================================= ERROR:HDLCompilers:87 - ../src/ip_block_wrapper.v line 270 Could not find module/primitive 'ip_block'

Any help appreciated. If I understood exactly what XST needs I could figure this out, but so far no go.

Thanks, Bob S.

Reply to
RobJ

You'll need to declare a black_box module that is compiled along with your design. This gives information about the port direction and port width. The instance declaration that you provided does not contain such information.

module ip_block ( port0, port1 ); input port0; output port1; endmodule

// synthesis attribute box_type of ip_block is "black_box";

RobJ wrote:

--
/ 7\'7 Paulo Dutra (paulo.dutra@xilinx.com)
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\_\/.\ San Jose, California 95124-3450 USA
Reply to
Paulo Dutra

Is the .ngo file in the project directory ?

If not, is the path to that directory listed in XST->Process Properties->Synthesis Options->Cores Search Directories ?

Brian

Reply to
Brian Davis

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