LDO Noise rejection

So you don't really need an LDO, you need a 30mA current source with a voltage cut-off ??

Think outside the box >:-} ...Jim Thompson

That's funny, in another thread I said something about connecting the source and gate making a FET into a resistor and the author of the circuit told me I knew nothing.

Does that surprise you? Selling a chip that does the whole job is a lot easier to sell than a chip that needs support circuitry which the competitor's chips don't need.

A lot of the stuff I've built over the years had to be tiny, handheld sort of stuff. If a switcher needed an external diode I would reject it out of hand because the recommended diode was often larger than the chip package. LT never understood my concern and the sales guy would say, "A diode is only a dime, if we put it on the die it is a lot more expensive". I guess they normally sell to folks who care about dimes rather than size... no, that can't be it. No one who cares about dimes designs in an LT part, lol.

I think over the years they did finally produce some low end buck switcher chips that don't need the diode.

He was right >:-}

Connect source and gate and it becomes OFF >:-}

(1) Read carefully the inequality I posted.

(2) Review elementary (i.e. Level=1) MOS theory. ...Jim Thompson

So a high value resistor then...

Yeah, I saw that. So why would anyone use a FET this way, with the gate and source connected?

It turns a depletion FET into a medium-quality current source. If the FET has a high enough V_DS rating, it's useful for input protection networks. The LND150 and BSS126 are good for that.

Cheers

Phil Hobbs

Ok, so Jim was wrong. I wish the circuit designer could have explained that at the time. He had a serious attitude and got all pissy about it when I said I couldn't tell if his schematic had an error or if this was really what he meant. Now I don't remember which thread it was in. lol

I wasn't wrong... you didn't read what I said, AND you don't know simple MOS theory. ...Jim Thompson

They didn't! You're still being bone headed and not accepting it.

If it were a depletion type if may be a valid thought, but since the lines didn't actually connect, it's still the same problem, you're being being headed.

Learn to read schematics.

Thank you and have a bad day.

Jamie

That isn't going to vindicate you, you're still wrong, because that isn't what was being done. Trying to find away to heal old injuries by hoping others forgot about it, isn't going to work.

Sorry for ripping open that old scare.., just let it rest and call it a battle that you lost.

Brush up on your schematic reading skills.

Jamie

It is very difficult to get good rejection at 1MHz in a regulator.

Use an LC input filter.

Kevin Aylward

?.....

Pretty much all "cmos" processes have a reasonable npn. Maybe at the really low gate length 65nm it may be an issue.

In pretty much all case, external components increase the size of the final product.

How do you expect to ship bendy iPhones if you make them thick.

This comment makes no sense to me. The thread is suggesting an nmos source follower, then an npn source follower is mentioned as an alternative, then your one here.

An npn will take up less room then an nmos for the same current and voltage drop.

Kevin Aylward

I had no idea that you had taken up walking the streets in your prior mentioned suspenders.

I agree. I actually use a fairly trivial, obvious extra fiddle in my LDOs to achieve better stability, yet which don't seem to be in the standard approaches.

Everyone seems to just copy the standard stuff in the books, with out going "how do I solve the actually problem"

Kevin Aylward

I did read what you wrote...

"C "It turns a depletion FET into a medium-quality current source."

Which of you is wrong?

Then there is the Jamie guy saying this isn't even the circuit. But I know I went around the barn with those guys and they swore that is exactly what the circuit was. It was hard to tell as the circuit was hand drawn and when I asked for clarification I mostly got insults rather than much in the way of explanation.

I am truly interested in learning how that circuit works, but either there is no one here who is willing to explain it... or maybe there is no one here who actually understands it. I dunno.

Lemme see...input: 8.5V to 9.5V, with that range, who gives a s* about frequency? You expect the "LDO" to _generate_ power to create an output of 9.0V when the input is 8.5V? Did you come from a different universe with different laws of physics?

You might read the thread a bit more to find that the voltage was a typo. He meant to say the output has to be above 5 volts.

Speaking of frequency, who the hell cares about attenuation at those frequencies if it's charging a LiPo?

Tim

I didn't say that. Depletion MOSFETs aren't commonly available in CMOS processes, AFAIK, and an ordinary enhancement device is indeed off at V_GS = 0. (I didn't really think it was necessary to further confirm that Jim knows how IC MOSFETs work.) ;)

Cheers

Phil Hobbs

Harry,

A half volt of 700KHz ripple is a lot easier to kill before it hits the chip, given the kinds of capacitors available nowadays to do just that. Requirement for local decoupling on inputs of ASICS is something designers are used to dealing with, so why not just make them do it? End users will likely just wimp out and apply an external LDO, anyways, if there's the slightest chance that a ($$)chip's performance will become unpredictable.

Getting internal load regulation will be hard enough, as is.

For really good dynamic load regulation a lossy ripple regulator on the output node can be run on the same regulation loop - but this thing is lossy already, so who's to complain?

RL