Lowest noise LDO ?

have a look at this shunt noise reducer

martin

How about following the regulator with an RC filter? You could use a large cap. Or, use an emitter follower, with a capacitively-decoupled potential divider feeding the base.

Try looking on the Wenzel website :

Patrick

What you are seeing at the output is probably a combination of noise, line and load regulation. The noise measurement is shown right in the datasheet, so it isn't faked. When under test, the line voltage is heavily filtered, and the load is just a resistor. If the load variation changes your "noise", then you are seeing load regulation errors, not noise. You can work on the output capacitor, i.e. lower ESR and/or more capacitance.

When you design a high PSRR regulator, the trick is generally to run the internal voltage reference off of a regulated supply. This can be the output of the LDO, or my preferred technique which is to create an additional shunt regulator inside the chip just to feed the voltage reference. Now if you have the headroom and budget, you can cascode LDOs. That is, use one LDO to provide the input voltage to another LDO.

Note that ultimately, the PSSR of the LDO at high frequencies is a capacitor divider made up from the capacitance of the pass element in the LDO and your output capacitor. Thus besides providing lower ESR at the output capacitor, you need lower ESL as well. This means a combination of different output capacitors.