I'm following this Appnote from National for using a ceramic cap. They have an NPN output driving the pass PNP. Would you recommend this.
AN-1482 LDO Regulator Stability Using Ceramic Output Capacitors
The regulator is stable with 20mV ripple when I use two 2.2uf Tant caps with 1.75 ohms esr. And a small integrator cap from the positive terminal to output and a small cap across the top of the divider.
I thought I would try to use one 805 ceramic mainly for it's small size.
The P-mosfet (U7) is connected source to input drain to output gate to MCP6002 output through a 10 ohm R.It is on a breadboard with some long leads.
Could you reccomend any other application notes or material that goes in more detail on stabilizing LDO's with ceramic output caps.
The Rcomp and Ccomp feedback needs to be negative i.e. it needs to go to the inverting input. This means you need a resistor in series with the Vref, or you add an NPN output transistor with suitable collector resistor to discharge the PMOS gate.
Note that in the above circuits that the overall feedback is negative and that the compensation is also negative feedback around the internal op-amp to the inverting input.
I think that is right, it looks like U7 is connected source to the positive voltage source and the drain to the output. That makes sense from a voltage drop point of view but it does add an inversion in the signal path.
That additional inversion causes confusion about which input is inverting and which is noninverting on the op-amp. Overall, the + and - switch but locally around the amp, they don't. In other words, the compensation is simply to the wrong input pin on the amp.
In general circuits with emitter or source follower outputs perform better than collector or drain outputs because the output impedance is lower even without feedback and no additional voltage gain is added to an already very high gain op-amp circuit.
All gain stages add an additional pole to the frequency response. Op-amps normally have two internal gain stages giving a two pole response with a maximum phase shift of 180 deg. When you add a third gain stage, you automatically add an addional phase shift ultimately to 270 degrees at the highest frequencies. You also give more total gain to deal with.
This makes compensation more difficult and adds concerns with overshoot, undershoot, rise time, and poor damping. I suspect that even if you get the circuit to work ok in the steady state, that it will have poor transient response and be unable to quickly and accurately respond to changes line and load conditions.
doesn't look right to me. If I read the time axis right (big if) it looks like it is oscillating at about 30kHz. I doubt that has anything to do with lead inductance. If true, I suspect amplifier stability is questionable for the reasons I mentioned above. It is ALWAYS troublesome to add another gain stage to an op-amp as that circuit does because of the increased loop gain and accumulating phase shift.
Those are simulated waves.The scope captures are pretty similiar though. Yes I think your right. I had it before so it was nice and smooth after the laod transient.Unfourtanetly I forgot the RC values. Theres about fifty loose caps and resistors from ecperimenting on my bench I'm sure I'll get lucky;).