High Vin LDO with truely low dropout in small package (long post)

Revisit the idea of using a buck switcher? That doesn't seem difficult over a mere 2:1 or so input range, and it will be a lot simpler than a switch+cap array, control logic, and an LDO.

John

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Did you look at the Texas Instrument TPS 6211X family?

Yes, simple, but very inefficient. At 100 mA it may not be so bad at around 50-60% typically, but at 10 mA or lower the efficiency goes to heck in a handbasket. The high Vin parts are all designed for 1.5 amps or higher so the efficiency goes south at lower currents. They typically get around this by using pulse skip mode or something similar, but we can't use that because we have to synchronize the freq to a common clock to help deal with the EMI.

Thanks for the thought though. Yes, I only wish someone would make a decent low current, high Vin switcher.

These are not LDOs. They are inductive switchers. The problem is efficiency. Since we have to use PWM mode only, the best it will do is reaching 80% at 100 mA. But the efficiency gets quickly worse at lower power levels. Below 6 mA an LDO is more efficient even at 17 volts and is still better at low Vin up to about 25 mA. Since this circuit will be powered 100% of the time the efficiency matters even at the lower power levels. The switched cap circuit can stay above 80% over all voltages and down to 1 mA I estimate.

Why do you you have to stay with PWM mode only?

In sci.electronics.design rickman wrote: ...

For the High Vin LDO did you look at the Zetex ZLDO Series? The Torex XC6202 Series might also fit if you only need 100mA and is cheaper and smaller.

A simple homemade hysteretic switcher should be efficient down to roughly zero current, if you allow a bit of ripple. As far as syncing with a clock to reduce EMI, well, I don't understand that... isn't it better to spread out the spectral lines instead of heaping them all on top one another?

John

PWM mode has to be used because the switching has to be synchronized and you can't do that in PFM.

Thanks for the suggestions. I don't know all the LDO makers and I figure I would get a few tips. The Torex part is not so low a drop out voltage at 670 mV, even at 30 mA it is 200 mV. The Zetex part looks like it will be a good choice although it comes in a larger package than I would prefer. It also is a fixed output voltage and the range is wide at about 3% tolerance. But this may well work. I don't know for sure what my range will be at the switcher output. We'll see when I prototype the circuit.

Two problems with that idea. First spreading the spectrum may or may not reduce the problem. For example, using a moving frequency for the clock may result in a test measurement that is lower, but does it really reduce the interference problem or does it just allow you to pass a test? The interfering spur is still the same amplitude, it is just moving while you test and so is integrated over a wider frequency range giving an average lower reading.

Secondly, in the case of power supplies, you will be generating spurs either way, sync'd or not sync'd. But if you sync all the supplies to the same clock, at least they are all creating the same harmonics. There are other ways to deal with the spurs since you can't get rid of them.

If it is easy to make a switcher with good efficiency at low currents, why aren't there chips available to do that? We get a fair amount of attention from the vendors because we sell a lot of units. They all try to sell me the same 1.5 Amp high Vin switchers with low efficiency at low currents. The TI part is the best one I have seen so far and it is terrible below about 30 mA.

What matters, other than passing the test?

Exactly. But I wasn't suggesting deliberate dithering or anything, just wondering what advantage there might be from syncing the switcher to the system clock.

Dunno. I did say "homemade."

John

(snip) Have you looked at National's LM2736 to do the whole job?

Efficiency at 3.3 V and 100 mA out is 70% with 18 volts in and 34% at 10 mA out. With a 5 volt supply those two efficiencies rise to 86% and 62%.

The slightly simpler LM2674

This one (LT3470) has even better efficiency at low current and a low parts count:

Output at 3.3 volts:

With 7 volts in and 1 mA out, 74%. With 7 volts in and 100 Ma out. 80%.

With 24 volts in and 1 mA out, 64%. With 24 volts in and 100 mA out, 72%.

I'm missing something here. The minimum input voltage is 7V. The output is 3.3V. Just how does this work out to a drop out voltage of 200mV? Can't you buck the input down to 4.3V, and use just about any LDO.

Having designed a few SMPS, there are plenty of gotchas. You are always better off buying an IC controller. There is much black magic in controller chips that the user never sees, mostly related to undervoltage lock-out and start-up situations.

Thanks for the tips, but I have looked at all of these devices as well as many more. This is the third time I have done this same power supply search for these parameters. If there was an inductive switcher out there that did a good job at 10 mA of current, I would have found it. But the combination of low current and high Vin seems to be deadly. In addition, all but a few of the high Vin regulators are non-synchrnous and many of those also require a boost diode. By the time you add the sizes of all these components you are using a fair hunk of real estate and not getting much in the way of efficiency.

Designing an inductive switcher may well be complex. But a multimode switched capacitor circuit is mostly a digital design along with careful control of the detailed timing. The only timing issue I am concerned about is that the P channel FETs must be driven through N channel FETs. These devices add much more delay to the path than the logic circuits will. To make sure there is no shoot through I will have to compensate these delays compared to the N channel FETs used on the low side of the caps. I may have to add N channel FETs to drive the N channel FETs just to equalize the delays.

But what I asked for help on was selecting an LDO that meets my requirements.

Yes, you missed that I am using a switched cap voltage divider in front of the LDO. Inductive switchers are too inefficient. Between input voltages of 7 to 10.5 I expect to use a 2:1 divider and higher ratios at higher voltages. This gives me 3.5 volts to the LDO if the switcher is optimal. I expect the switcher drop out to be minimal as the FETs I am using are sub ohm resistance. I found nice small complementary FETs in a 2x3 mm package rated for healthy currents and low voltage drive. So assuming I loose 100 mV in the switcher and 200 mV in the LDO, I can still get 3.2 volts out of the LDO. If the tolerance (including set resistors) is +-3%, I can set it for 3.1 volts and it will not be below 3.0 volts or above 3.2 volts meeting all the limits.

I do have some concerns about the losses in the switcher. But if they are too high to run the switcher and LDO from 7 volts, I can always add a 1:1 mode for the low end of the input voltage.

Just out of curiosity - what frequency will the switcher run?

Regards Rocky

The LP2951/LP2954 family get close. Micrel & Advanced Monolithic do 'better' versions of these, with -20/+60V ip.

You could also look at placing the LDO _before_ the switch-cap, since you say that has low Rs. That halves the LDO current, and also makes the dropout a smaller % of higher voltage.

Also, because you DO have a higher voltage, that opens up boosted gate drive schemes, most often found in higher current regulators.

Have you looked at LED drive Switch modes ? - these are getting smarter all the time, and often have mode changes, and are designed to deliver low load currents, at high efficencies - because they target handheld apps.

-jg

A switcher in burst mode has less transients than in PWM mode. Thus generates less EMI. If you want low EMI, then you have to choose a switcher with controlled/slower transients.

Rene

If you're worried about 10mA why on earth are you considering using a CPLD for anything...?