another LDO

Seriously, I need another LDO for a new gadget. It needs to work down to maybe 1 volt drop, and needs to be very accurate, especially longterm drift and TC.

How about this?

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Joerg will be pleased to see a depletion fet. Jim will find something to whine about.

It might be fun to power the opamp from the +10 rail, if I could prove that's safe at startup. That does keep from enhancing the fet and preserves its Idss current limit. I only need about 50 mA out, with a nearly constant load. I could even add a source resistor.

Maybe I should add a gate resistor, just in case the fet wants to oscillate on its own.

I guess I could also servo the ADJ pin of an LM1117.

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John Larkin                  Highland Technology Inc
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John Larkin
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Running the opamp off +10 is probably too cute for its own good.

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John Larkin                  Highland Technology Inc
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John Larkin

I don't see the advantage of a depletion fet. If anything, it insures the regulator will go overvoltage on start up since the fet is conducting at zero time. Certainly true for a high DV/DT on the supply rail.

A mos pass device is good. Roll your own regulators is usually asking for trouble. COTS devices have well behaved start up, short circuit protection, and often reverse power protection.

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miso

A regular n-channel mosfet won't have enough gate drive available. I guess a p-channel would be OK, but I'd need to add some sort of current limit. A commercial LDO won't be as accurate as I need; I'd like to hold a few hundred PPM over time and temperature, and tracking the DAC reference is good here, too. A powerup overvoltage blip wouldn't bother me... there's only 12 volts available, and that wouldn't damage anything.

Probably the LM1117 thing is more prudent, with the opamp powered off

+12. I've tried to damage LM1117s by doing rude things to their ADJ pins and they didn't care.
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John Larkin                  Highland Technology Inc
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John Larkin

At 12 ohms on resistance that's iffy. Depends on what the opamp output does when at only 1-2V supply. If it won't come up enough then you'd lose the 10V output.

You could also use a series resistor towards the gate and then a diode from gate to drain. Then it won't enhance to more than 700mV or so.

But with a depletion mode FET you get a stable LDO, why give that up?

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Regards, Joerg

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Reply to
Joerg

Stability. It behaves like the usual follower structure of a non-LDO.

John, the depletion mode FETs from Infineon cost less, in case that's a concern.

Au contraire, monsieur.

Yeah, right. I've seen a lot of COTS LDOs with behavioral issues. All the way to going *PHUT* after a while.

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Regards, Joerg

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Joerg

There's always the LM10. Supply voltage from 45V down to 1V and includes a 200mV reference voltage source.

Farnell still stocks it.

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-- Bill Sloman, Nijmegen

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Bill Sloman

2V drop is within LM317 range at low currents.

Cheers

Phil Hobbs

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Phil Hobbs

"2V" is now called "LDO" ?? ...Jim Thompson

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| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
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Jim Thompson

I prefer the 1117. It's very similar to the 317 but has somewhat lower dropout. 317 is a Darlington, and 1117 is a pnp-npn pair, what we used to call a "pseudo-PNP." I think there's somebody's name attached to that.

I'm doing a mess of DAC-trimmed current sources, to make fast ramps, and I can grossly simplify everything if I can make a really good +10 supply.

I've used 1117s as power amps before, and they work great.

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John Larkin                  Highland Technology Inc
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John Larkin

But read the fine print. Quote "The ESR of the output capacitor should range between 0.3?-22?".

So what if all the ceramic bypass caps for the stuff that's connected add up to a few uC and literally zero ESR? Nah, not my cuppa tea.

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Regards, Joerg

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Reply to
Joerg

I posted the schematic of the 1117 version, with a 22uF tantalum. Tantalums are perfectly safe if you treat them right.

I haven't seen any problems loading an 1117 with a tantalum paralleled by a bunch of ceramic bypass caps. Seems like the tantalum ESR fixes things nicely. I expect maybe 1 uF of additional ceramics in this case.

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John Larkin                  Highland Technology Inc
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John Larkin

Horrible, ancient, expensive, won't work here.

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John Larkin                  Highland Technology Inc
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John Larkin

Not in the stuff I often design.

I've heard the 1117 to be pretty well behaved but in mission critical designs I like to have guaranteed specs. My five votes per household go towards the depletion mode solution. So when's the results show?

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Joerg

Does not look like you need the RC network in the feed back on this one however, if you couple a cap across the top R for the divider, you can get some leading phase to over come the gate charge lag.

I've done such a reg before but I used a enhanced NMOS with a video type op-amp. I only got ~ 20 uv ripple on the output using some where around a .5 amp ripple load. This was a while ago so memory maybe a little short here.

It's possible the depletion type may behave differently, I kind of thought they were inherently higher in Ron ? I didn't look up the one you have in your schematic.

Jamie

Reply to
Jamie

Lag?

You can get some pretty mean ones but then they are expensive:

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Depletion mode is almost forgotten these days. I had one guy exclaim in a design review "This ain't gonna work!" and then pointing out that there wasn't any bootstrap stuff. Took the whole group by surprise when I explained why we don't need that.

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Regards, Joerg

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Reply to
Joerg

Certainly ancient, not actually horrible. Not cheap but occasionally worth the money. "Not invented here" so we'll never find out if it might have worked.

-- Bill Sloman, Nijmegen

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Bill Sloman

It won't put out enough current, and its temperature drift wouldn't meet my requirements.

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John Larkin                  Highland Technology Inc
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John Larkin

Yes, lag. The over all effect of gate charge causing response issues in a circuit of that type. If you put a cap in the front end of the op-amp from the process value (output), You can get some lead, otherwise know as the (D) term in the PID loop.

In other cases, you can get the opposite effect where the error value is actually already leading in error and thus we need to deal with that in a different way.

Calculating the phase margin(error) can lead to all sorts of issues when the source of the calculation may not be a stable one, like variable loads for example. The load causing phase error to move. In such cases, unity stages are usually employed to isolate that problem so that the phase margin is constant. It just so happens in some circuits it works out nicely where you can rely on a reference point to be constant and others, not so much.

This of course, is with the use of a NMOS (enhanced mode) fet, I have not tried this with a depletion mode type. I can only assume the effects should be some what the same in this follower reg circuit.

I understand the process for making power depletion types are more expensive and less reliable. Most likely why you don't see them in a lot of designs.

The last circuit I did like this was with 500V NMOS fets for a 250V supply that needed to be variable +/- 50volts with a sine wave signal of 1khz modulating it at times and constant DC at other times.

Jamie

Reply to
Jamie

So, what does that mean "Not Invented here" ? Does that mean it has to be inferior?

Jamie

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Jamie

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