1. Home
  2. Electronics Design
  3. LDO- CMOS IC design

LDO- CMOS IC design

hello

i've met this problem during simulation, and hope you can say something about it.

these are two links:

  1. simple circuit rewriten in ltspice
    formatting link

  1. time response

formatting link

the opamp is Leveraged Current Mirror Op Amp. time response should be equal to 1us when programmed output changes from 0.8V to 1.4V.

what can limit this response? from 0.8 to 0.9V it rises rapidly.

i tried to use buffer, to achieve wide bandwidth. 7Mhz gives almost the same results (2us is tke limit) as 1Mhz without buffer, but better slew rate. I've chcecked resistors and small transistors influence, but it doesn't improve the response in significant way.

The main spec is low current unfortunately, so the are less degrees of freedom.

any help appreciated

regards

Reply to
jutek
Loading thread data ...

For a current source, everything above 1MHz is a good. Limiting, in real world, is the gate capacitance of the PMOS. How big is it and how much current can you spend for it ?

Rene

--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net
Reply to
Rene Tschaggelar

PMOS is very big W=100m L=0.5u

the quiescent current should be as low as possible, about 100-150uA.

Reply to
jutek

No such term as "Leveraged" Current Mirror Op Amp. What do you mean?

Too little gate drive current. On resistancexCload too large, small signal BW insufficent.

Go and work out Cin of the fet. Caclculate dv/dt=i/c. Can your buffer supply this amount of current?

How big is the load capacitor?

A 0.1ohm output on resistance of the fet and 10uf is 1us time constant.

I would guess that you are not driving the gate with enough current. You really only have two main choices. Not enough gate drive current, or too big a cap load. Typicallly, one can get the small signal response faster than any current limit effects.

It can be tricky to get a decent AB drive to the gate of a pmos at low bias currents and at low supply voltages...

Kevin Aylward

snipped-for-privacy@anasoft.co.uk

formatting link
SuperSpice, a very affordable Mixed-Mode Windows Simulator with Schematic Capture, Waveform Display, FFT's and Filter Design.

"There are none more ignorant and useless,than they that seek answers on their knees, with their eyes closed"

Reply to
Kevin Aylward

i mean

formatting link

gate's capacity is about 200p and during slew rate, opamp drives it with more than 2mA current so you're surely right, it's caused by too much load capictor. but if i decrease it, the zero related to this capacity goes to higher frequencies and worsen phase margin.

yes, i thought about class AB, but can find any proper circuit, which can work also for low vdd. can you give me any advice about class AB? it would be the best solution in this situation

thanks and regards

Reply to
jutek

i mean

formatting link

gate's capacity is about 200p and during slew rate, opamp drives it with more than 2mA current so you're surely right, it's caused by too much load capictor. but if i decrease it, the zero related to this capacity goes to higher frequencies and worsen phase margin.

yes, i thought about class AB, but can't find any proper circuit, which can work also for low vdd. can you give me any advice about class AB? it would be the best solution in this situation

thanks and regards

Reply to
jutek

one more thing

during high load conditions on resistance is 1/gds=1/30.6766m=32.5981

output resistance is 1/(gds+1/Rl)=9.79 ( Rl=14 )

Cl=1uF so this time constant should be about 10us but is about 2us

Reply to
jutek

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.