LDO- CMOS IC design

For a current source, everything above 1MHz is a good. Limiting, in real world, is the gate capacitance of the PMOS. How big is it and how much current can you spend for it ?

Rene

PMOS is very big W=100m L=0.5u

the quiescent current should be as low as possible, about 100-150uA.

No such term as "Leveraged" Current Mirror Op Amp. What do you mean?

Too little gate drive current. On resistancexCload too large, small signal BW insufficent.

Go and work out Cin of the fet. Caclculate dv/dt=i/c. Can your buffer supply this amount of current?

How big is the load capacitor?

A 0.1ohm output on resistance of the fet and 10uf is 1us time constant.

I would guess that you are not driving the gate with enough current. You really only have two main choices. Not enough gate drive current, or too big a cap load. Typicallly, one can get the small signal response faster than any current limit effects.

It can be tricky to get a decent AB drive to the gate of a pmos at low bias currents and at low supply voltages...

Kevin Aylward

snipped-for-privacy@anasoft.co.uk

"There are none more ignorant and useless,than they that seek answers on their knees, with their eyes closed"

i mean

gate's capacity is about 200p and during slew rate, opamp drives it with more than 2mA current so you're surely right, it's caused by too much load capictor. but if i decrease it, the zero related to this capacity goes to higher frequencies and worsen phase margin.

yes, i thought about class AB, but can find any proper circuit, which can work also for low vdd. can you give me any advice about class AB? it would be the best solution in this situation

thanks and regards

i mean

gate's capacity is about 200p and during slew rate, opamp drives it with more than 2mA current so you're surely right, it's caused by too much load capictor. but if i decrease it, the zero related to this capacity goes to higher frequencies and worsen phase margin.

yes, i thought about class AB, but can't find any proper circuit, which can work also for low vdd. can you give me any advice about class AB? it would be the best solution in this situation

thanks and regards

one more thing

during high load conditions on resistance is 1/gds=1/30.6766m=32.5981

output resistance is 1/(gds+1/Rl)=9.79 ( Rl=14 )

Cl=1uF so this time constant should be about 10us but is about 2us