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Xilinx PAR -- WARNING:Route - CLK Net may have excessive skew...

Greetings,

I am implementing a design whose system clock is generated by an MGT (the TXOUTCLK pin), based on higher frequency differential reference clock inputs to that MGT. The frequency generated at TXOUTCLK is correct, but the issue is that Xilinx ISE (7.1i, SP4) does not route this clock as a CLK Net.

The particular error, generated after PAR, is "WARNING:Route - CLK Net: net_name may have excessive skew because xx NON-CLK pins failed to route using a CLK template."

This design cannot tolerate the max skew that is reported (about 20% of a period), or the resulting max delay of about 40%. How can I force this net to use the CLK template I specified in the UCF, or otherwise remedy this issue?

Thanks much, Julian Kain

Reply to
Julian Kain
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This error message usually means there are non-clock loads in the design. This can happen when the clock signal is used as a gate (LUT) input. Normally in a fully synchronous design only clock or latch gate inputs of the CLB or IOB would connect to the clock route.

If you have the FPGA editor I would suggest looking at the post place-and-route design and see how the clock was actually routed. If it uses global resources for all of the clock loads and only local resources for gated loads you may actually have lower skew to the important loads than reported. If you are actually gating this clock to deliver to some clocked loads, you should try to change the design to use clock enables rather than gated clocking.

Reply to
Gabor

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