Whiel running modular design i get a single error at the end of active module implementation phase => Unrouted net GLOBAL_PSEUDO/CLK. The thing abt. this net is that it is inserted by the mapper alongwith a bunch of other signals that help the router route the inter-module signals properly. This CLK is what goes to the intermodule signal registers that map is inferring automatically at the boundary of the module. So this signal is not really a part of my design. And clearly there are plently of empty areas around it as is evident when viewing it in FPGA editor.
Any pointers?
regards, nachiket.