If I register all my signals in the IOB and use the global clock, why is the clock to out different on different outputs? Why does my clock to out vary from compile to compile?
clock to out ranges 4.664ns to 5.355ns Is this just skew in the global clock? Can it be controlled with constraints?
I am using Synplify 7.2, XST 5.2.03, Win2K SP4, XCV1000E-6FG860C
Alan Nishioka snipped-for-privacy@accom.com