Net hierarchy with Xilinx 9.1


I ran into a small problem while trying to use a UCF file created for ISE 8.2 within EDK 9.1. I had a few INSTs and NETs relatively deep within the design's hierarchy:

INST "ioring/U_top/u_adc_clk_dcm" FACTORY_JF = "ABCD"; NET "ioring/U_top/sdram_clk_sig" TNM = sdramclk;

I get an error from Xilinx stating it can find neither the instance nor the net when trying to implement these constraints. Looking around, I found the solution for the INST using the syntax:

INST "ioring/*U_top/* u_adc_clk_dcm" FACTORY_JF = "ABCD";

But It didn't work for the net (sdram_clk_sig is a std_logic signal within the U_top instance). Anybody knows the correct syntax to access a net within such hierarchy with Xilinx 9.1?



Reply to
Louis Dupont
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You could try to use FPGA Editor to browse the design and identify the correct name. XST most likely created slightly different names and this is why it's not working anymore. It's a pain but I don't know any other way unfortunately...


Reply to
Patrick Dubois

No, but maybe you could generate the post-synthesis simulation model, and search it to find the net name.

If the net has been optimised away or combined with another functionally equivalent one, searching for components connected to it should give you the information you need.

- Brian

Reply to
Brian Drummond

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