I ran into a small problem while trying to use a UCF file created for ISE 8.2 within EDK 9.1. I had a few INSTs and NETs relatively deep within the design's hierarchy:
INST "ioring/U_top/u_adc_clk_dcm" FACTORY_JF = "ABCD"; NET "ioring/U_top/sdram_clk_sig" TNM = sdramclk;
I get an error from Xilinx stating it can find neither the instance nor the net when trying to implement these constraints. Looking around, I found the solution for the INST using the syntax:
INST "ioring/*U_top/* u_adc_clk_dcm" FACTORY_JF = "ABCD";
But It didn't work for the net (sdram_clk_sig is a std_logic signal within the U_top instance). Anybody knows the correct syntax to access a net within such hierarchy with Xilinx 9.1?