FPGA with 2 JTAG ports

I am not exactly sure what you are suggesting. Are you proposing that there is one boundary-scan TAP connection that goes through the PROM to the FPGA and another that goes directly to the FPGA without involving the PROM?

If that this the case, since there is in actuality only one physical TAP on the FPGA, that means there will only be one set of TMS and TCK connections which means that if you are trying to access the FPGA-only TAP you will have the PROM traversing through its state machine and when you try to shift data into the FPGA the PROM TDO will be active and shifting, as well.

I suppose you could add some extra control logic to guarantee safe operation of the two TAPs but in the end, why would you?

If you have a single chain of a PROM followed by an FPGA you can address either device by BYPASSing the other. You can program the FPGA with a bitstream file with the PROM in BYPASS or program the PROM with an mcs or exo file with the FPGA in BYPASS.

Does that help?

snipped-for-privacy@gmail.com wrote:

Hi Neil,

Thanx. We understood what ur suggesting but then the problem is both the JTAG ports are connected to the FPGA. We dont understnd the purpose of the 2nd JTAG port which is directly connected to the FPGA thro TMS, TCLK, TDI and TDO pins.

Also the 1st JTAG port sends TMS, TCLK, TDI and TDO to the PROM and the PROM gives a Prog_b to the FPGA...which is what we are familiar with.

Thanx again for ur reply and if u can think of some reason why there might be 2 JTAG ports shoot me a email.

Regards,

- Shailesh

Neil Glenn Jacobs> I am not exactly sure what you are suggesting. Are you proposing

that

to

TAP

FPGA-only

when

address

a

mcs

ports?

similar case is used in Altium livedesing, there a special 2 port Xilinx compatible cable is used the xilinx JTAG pins go the FPGA normal JTAG pins the secondary JTAG goes to

4 general purpose pins on the FPGA, those 4 pins are connected to JTAG TAP controller ip core inside the FPGA (made from logic resources), this secondary 'soft TAP' is used to control the on chip logic analyzer and that kind of stuff

not sure if that was the answer you wanted

antti

Hi Antti,

The secondary port which is coonected to the FPGA general purpose pins as u suggested, does it require some programming file?

Or its just control to and from the FPGA.

Thanks a lot,

- Shailesh

Antti Lukats wrote:

directly

those

Xilinx

goes to

TAP

'soft

schrieb im Newsbeitrag news: snipped-for-privacy@z14g2000cwz.googlegroups.com...

no, well it doesnt require any configuration file at least. its just an additional user access port into the FPGA and its up to the application how it is used. it could be connected to some onchip or offchip memories and your application could use it to download some data to memory, etc..

however the same functionality can be achived over the main jtag port as well, by using the BSCAN primitive what is availabe in most modern FPGA's.

I think that Altium uses the second soft TAP just to make their life easier, the soft TAP can be implemented to be compatible on any FPGA being it from xilinx altera or actel, while the use of main JTAG over BSCAN is vendor dependant always.

uses the main JTAG and BSCAN to control the on-FPGA counters, it uses JTAG HUB

and works equally well on xilinx and altera chips (actel and lattice support is not added yet)

antti

I think I really don't understand the original question. Are you asking "if" you could instantiate 2 TAPs on a single FPGA? Or are you asking "why" would you instantiate 2 TAPs on a single FPGA.

If the question is "if" then the answer is, as Antti L. suggested, you could use the single dedicated FPGA TAP and then create a separate TAP and TAP controller out the FPGA fabric and general purpose pins. You could then connect that "soft" TAP to whatever you needed in the device. It would operate independently of the dedicated FPGA TAP.

If the question is "why" my answer would be "I don't know - just because you can, I suppose" :-) There may be some specific application for which that makes sense, I just can't think of a good one.

My previous posting was trying to describe how you could create two separate access points on a single boundary-scan chain consisting of two devices connected to one another in the usual manner.

snipped-for-privacy@gmail.com wrote: