Jtag thousands fpga

Well, connector attach/detach time is a problem. Instead of a connector, use an IRDA receiver or transceiver, and you can send all the program commands from an IR LED searchlight, to as many powered boards as you can gather in the illuminated spot...

The receiver, and the associated logic, are added cost; the program fixture and/or board connector for other program scheme, is a savings.

What FPGA exactly ??

On a sunny day (Tue, 23 Jun 2015 13:37:05 -0700 (PDT)) it happened whit3rd wrote in :

Don't you want a verify?

Verification wasn't in the original spec.

In mass programming I woudn't skip the verification step. Manually inspecting (root cause analyses + paperwork) one failed unit out of

There are lots of details to this question. If they are all the same FPGA with the exact same bitstream, they can be programmed in parallel, although that will require one data return signal (TDO) for each of them. Daisy chaining won't improve the programming time since each one is done independently.

If they all have different programming, but are the same device, then it may be possible to have separate TDI and TDO signals yet program them in parallel using the same TCK and TMS signals.

My last thought is to question the need to program them all at the same time. It is very unlikely that they are all available at exactly the same time, so why wait on programming some before you program the others. If there is a problem with manufacturing do you want to wait until thousands are made before you test them and find the bug?

I have a few hundred of my FPGA board made at the same time and at one time I did all the testing. I would show up with my test setup as the boards were coming out of cleaning and final inspection a couple dozen at a time. I would program and test them about half as fast as they could inspect them. I never found a need for a mass programming fixture. I think it take about 30 seconds to program one Flash type, small FPGA. Most of that is erase time.

ection is active.

Fast reconfiguration diferent bitstreams, the biggestfpgas

Why don't you provide more info on your setup and ask this in the FPGA group? what flexibility do you have in what you are doing? What limitations do you have? Are you talking about RAM base devices that have to be reprogrammed every time they power up?