Master Xilinx FPGA like Jtag bridge.

|---------|-TMS----|------------|-TMS---- | FPGA 0 |-TCK----| |-TCK---- | |-TDO----| |-TDO---- |---------| | |-TDI---- | | | TDI | | | | | | | MASTER FPGA| | | | TDO | | | | | |---------|-TMS----| | | FGPA 1 |-TCK----| | | |-TDI----| | |---------| |------------|

On Saturday, February 25, 2017 at 11:21:13 AM UTC+6, snipped-for-privacy@gmail.com wrote :

TDI connect to master fpga, master fpga has TMS TDI TDO TCK connected and w orking to pc normally, it need to make connection JTAG of two fpgas to othe r 4 ports or somehow can connect to master's jtag port ?

| |---------|-TMS----|------------|-TMS---- | | FPGA 0 |-TCK----| |-TCK---- | | |-TDO----| |-TDO---- | |---------| | |-TDI---- | | | | | TDI | | | | | | | | | MASTER FPGA| | | | | | TDO | | | | | | | |---------|-TMS----| | | | FGPA 1 |-TCK----| | | | |-TDI----| | | |---------| |------------|

Why do you want the master FPGA to control the others rather than loading them all in one chain? Connect all TMS and TCK lines in parallel and connect all TDI and TDO in one big daisy chain. If the slave FPGAs are loaded by the master, where will the data come from?

rote:

nd TDI connect to master fpga, master fpga has TMS TDI TDO TCK connected an d working to pc normally, it need to make connection JTAG of two fpgas to o ther 4 ports or somehow can connect to master's jtag port ?

It is reverse engineering, someone did this but i just want reuse board onl y

The JTAG signals to the master chip, do they connect to general I/Os as well as to the FPGA JTAG signals? Or just JTAG or just I/Os?

You didn't say where you expect the data to come from to program the chained slave FPGAs. Is it supposed to come from the main JTAG port as if it was talking to the slave chain? Or will the master FPGA have a separate interface from an MCU or a Flash chip?

What is your overall plan?

and TDI connect to master fpga, master fpga has TMS TDI TDO TCK connected and working to pc normally, it need to make connection JTAG of two fpgas to other 4 ports or somehow can connect to master's jtag port ?

only

Hi, i am also doing same thing and also have same question )))). I think fi rst need program master FPGA and then normal masters JTAG can be used as JT AG for other tributary fpgas . may be/

and TDI connect to master fpga, master fpga has TMS TDI TDO TCK connected and working to pc normally, it need to make connection JTAG of two fpgas to other 4 ports or somehow can connect to master's jtag port ?

only

Slave FPGAs connects to USER I/O ports. for example: TMS of salve FPGA chip connects to user i/o pin CC TDI of slave FPGA chip connects to user i/0 pin VRP TCK of slave FPGA ship connects to user i/o pin CC

What do you connect the user I/O of the master to internally? If you try using the JTAG on the master it will control the master, no?

Perhaps you are looking for something similar like Altera JAM Player for embedded.

Take a look here

There is pice of C code able to send chip image from embedded system to another fpga.

Unfortunatell I don't know X as good as I would like to.

BR

Adam

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I dont know C