hi all!
what hapens when i send a code written in vhdl through jtag to the fpga? if anyone can tell me in detail the process..or suggest some good links for the same. regards
ashu
fpga programming
May 01, 2006
3 Replies
happens exactly the same thing when you send code written in verilog.
Antti
Ashu,
You don't send code through the JTAG. Your code needs to be transformed into a bitstream that completely describes how all the bits in the FPGA should be set (describing what is in all of the LUTs and how they are connected). This bitstream is what you send through the JTAG. There are a number of steps between entering your code and generating this bitstream. Go to the Xilinx or Altera sites (or just google) and search for 'design flow'. Good luck,
Joey
Ashu, you have to ask the wizard of OZ
Aurash
snipped-for-privacy@gmail.com wrote:
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