Hi all,
to implement something like a passthru mode, we want to directly connect two XAUI ports inside the FPGA. The FPGA is a Xilinx Virtex-6.
Therefor we did instantiate two XAUI-cores and connected txd/txc from one core with the rxd/rxc from the other core and vice versa. Because both cores use a different refclk we simply added two synchronizer FFs in between.
In our test-design this works. But when added to the full design this code fails (the data after the synchronizer FFs seems scrambled). Is it at all possible to directly connect two XAUI cores? Is it possible to connect two blocks with the same clock frequency but - probably - different clock phase just using 2xFFs?
Kind regards, /gw