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Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
Hi Rick,

First of all, I have to appreciate your following guessing:
"If you can perform an equality comparison without using gates, that will b
e of tremendous value in logic design.  Instead of using conventional gates
 all logic can be decomposed to an expression using equality comparisons (t
he equivalent of the XOR applied to bits followed by an OR gate).  So if yo
u can perform the not equal comparison on a multi-bit word without gates, t
hen every digital logic design can be implemented with no logic gates at al
l!   "

But You are wrong in guessing my invention without any logic bases.

1. There is no comparison at all.

2. I use another trick to avoid any comparison for a state machine circuit  
and reach a conclusion that you need comparison to achieve.

3. The trick seems to be non-obvious to you now.  

But don't worry, your conclusion is wrong too:  
"obviously what you said is not true.  So I must be misunderstanding you."

Weng

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Wednesday, January 9, 2019 at 6:23:44 PM UTC-5, Weng Tianxiang wrote:
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Perhaps Rick is wrong as you state (or maybe not), but I am not.  You have  
disclosed enough to discern what you think is the important idea to patent  
(although I don't pretend to know all that you may claim from that idea). S
ince you cannot disclose until you hear about publication, I won't disclose
 either.

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t and reach a conclusion that you need comparison to achieve.
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But in fact the 'trick' as you call it is obvious and also, unfortunately f
or you, the idea is in fact old prior art that you are simply not recognizi
ng. But maybe the PTO won't pick up on it, or maybe you'll find someone to  
part with $$ for what you will be marketing as a 'new' idea or maybe, if th
e patent is granted, you'll get challenged in court and lose. Time, as they
 say, will tell.

Kevin Jennings

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
Kevin, Can you give me a link to the prior art idea?

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Wednesday, January 9, 2019 at 10:26:39 PM UTC-5, Weng Tianxiang wrote:
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Sorry, I'm not going to prior art research for your patent application for you.

However, I will suggest that you tend to take a very narrow view of some topic, such as a state machine, and appear to ignore applicable work that is more general, of which your 'state machine' is simply a subset.

Kevin Jennings

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Wednesday, January 9, 2019 at 6:23:44 PM UTC-5, Weng Tianxiang wrote:
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 be of tremendous value in logic design.  Instead of using conventional gat
es all logic can be decomposed to an expression using equality comparisons  
(the equivalent of the XOR applied to bits followed by an OR gate).  So if  
you can perform the not equal comparison on a multi-bit word without gates,
 then every digital logic design can be implemented with no logic gates at  
all!   "
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t and reach a conclusion that you need comparison to achieve.
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"

Ok, I am reading your code.  So you are saying your code is not what you me
an.  Got it.  


  Rick C.

  ++ Get 6 months of free supercharging
  ++ Tesla referral code - https://ts.la/richard11209

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Saturday, January 5, 2019 at 8:23:43 PM UTC-5, Weng Tianxiang wrote:
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ore than 10 states must have a clock gating function to save power consumpt
ion:  

That is your unsubstantiated claim, not a fact.

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t be generated to keep the state unchanged and save power consumption.
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Any perceived lower power consumption has very, very little to do with the  
fact that the state does not change.  A flip flop that is clocked but does  
not happen to change its output does not consume much power.  The power is  
needed to charge/discharge the loads that are being driven.  Any decreased  
power consumption would have to do with the decrease in power in generating
 the clock input to the flip flop.  But shifting from a common clock to add
ing a gate that generates a clock probably does not lower power since the s
ame number of clock signals are being generated.  If the gated clock routin
g is a higher capacitive route then when using a free-running clock then yo
u can consume more power.  This is the result when trying to implement gate
d clocks in FPGA.  ASIC will be different.

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may not be necessary because too few state machines are implemented in any  
normal application.
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As I pointed out to you back in 2010 (I think), implementing what you descr
ibe in an FPGA results in an increase in power consumption.  I provided you
 with all of the details for your sample design.  The results of that analy
sis are not "because too few state machines are implemented", it is because
 gated clocks in FPGA use more power, not less.  Again, that was with your  
sample design of that time which appears to be the same thing you are reusi
ng here.

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 as follows after the post is posted:
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I noticed that you did not show the actual gating of the clock, only the ap
parent usage of a possibly free running clock.

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Also, the following 'elsif' is not necessary even though your comment says  
it is.  No worries though, synthesis tools should optimize out the 'elsif'  
and leave the assignment 'WState <= WState_NS;' on every clock.  If the t
ool somehow leaves it in, then there will be an increase in power consumpti
on due to use of additional logic required to implement 'elsif WState /=  
WState_NS then'.  That increase would need to be counted against any power  
savings that you think you're achieving.  Again, it would probably be worth
while for you to do some analysis prior to posting and claiming...but after
 all these years of not acting on this advice it doesn't appear that you're
 willing to make that behavioral change.
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sary!
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I suspect that you did not actually test any of this prior to posting and c
laiming since the code is not complete and does not compile...as usual.

Kevin

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Monday, January 7, 2019 at 5:11:05 AM UTC-8, KJ wrote:
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 more than 10 states must have a clock gating function to save power consum
ption:  
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not be generated to keep the state unchanged and save power consumption.
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e fact that the state does not change.  A flip flop that is clocked but doe
s not happen to change its output does not consume much power.  The power i
s needed to charge/discharge the loads that are being driven.  Any decrease
d power consumption would have to do with the decrease in power in generati
ng the clock input to the flip flop.  But shifting from a common clock to a
dding a gate that generates a clock probably does not lower power since the
 same number of clock signals are being generated.  If the gated clock rout
ing is a higher capacitive route then when using a free-running clock then  
you can consume more power.  This is the result when trying to implement ga
ted clocks in FPGA.  ASIC will be different.
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n may not be necessary because too few state machines are implemented in an
y normal application.
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cribe in an FPGA results in an increase in power consumption.  I provided y
ou with all of the details for your sample design.  The results of that ana
lysis are not "because too few state machines are implemented", it is becau
se gated clocks in FPGA use more power, not less.  Again, that was with you
r sample design of that time which appears to be the same thing you are reu
sing here.
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DL as follows after the post is posted:
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apparent usage of a possibly free running clock.
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s it is.  No worries though, synthesis tools should optimize out the 'elsif
' and leave the assignment 'WState <= WState_NS;' on every clock.  If the
 tool somehow leaves it in, then there will be an increase in power consump
tion due to use of additional logic required to implement 'elsif WState /
= WState_NS then'.  That increase would need to be counted against any po
wer savings that you think you're achieving.  Again, it would probably be w
orthwhile for you to do some analysis prior to posting and claiming...but a
fter all these years of not acting on this advice it doesn't appear that yo
u're willing to make that behavioral change.
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essary!
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 claiming since the code is not complete and does not compile...as usual.
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Hi,

There are several experts responding to my post. Thank you. Noticeably I do
 not find Hans of www.ht-lab.com giving his opinion. Usually his opinion is
 reasonable and informative and he knows many things outside the FPGA chips
 beyond my knowledge.

Here is the background for the purpose of my post:
1. On 12/31/2018 I filed a non-provisional patent application. I asked for  
earlier publication. The publication will happen about 14 weeks later since
 its filing date.

2. On 01/06/2019 I sent it in almost the same version as a regular paper to
 IEEE Transaction of circuits and System for publication. The review proces
s may take up to 3 months.

Because IEEE Transaction strict restriction on the paper's originality, I c
annot disclose any details about my invention until the transaction agrees  
to publish my paper 3 months later or rejects my paper in 1 or 2 weeks.

Here are some facts of my invention:
1. The logic used to generate a state machine with clock gating devices is  
almost the same as conventional method would generate, or maybe even simple
r than conventional method.

2. I don't know how CPU deals with its 100,000*4 FFs clocking scheme used i
n state machines for the Cache II control. If they don't care about the pow
er saving or they have implemented some scheme in the implementation, my in
vention would be of few values, or otherwise it would be worth million of d
ollars.

3. My post's purpose is to test if such invention is of any value, not abou
t how to implement a state machine with clock gating function.  

4. After my application is published 3 months later I will immediately regi
ster and sell the application at http://www.ast.com/interested-in-selling-t
o-ast/. I know the website because Google refers to the website and indicat
es they are a member of the site. I expect that Intel, IBM, AMD, Apple may  
also be the members of the website. The site asks for the selling price dur
ing registration. So it is important for me to assess my invention's value  
properly.

5. I think no developing persons at Intel, IBM, AMD, Apple would visit this
 website, not mention taking part in the discussion of my post.

6. I hope I will discuss the invention in more details 3 months later befor
e my registrations in the patent selling website.

7. Xilinx chip has clock enable signal built into its cell block, one CE in
put for 8 registers in the block. Altera may be in the same situation. So c
lock enable is never a new thing and we don't have to pay attention to how  
the clock trees work. For a CPU design, in my opinion, logic design and clo
ck tree design are 2 separated domains one after another, and logic designe
rs never have to pay attention to the clock trees.  

Thank you.

Weng


Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Monday, January 7, 2019 at 2:21:51 PM UTC-5, Weng Tianxiang wrote:
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ng more than 10 states must have a clock gating function to save power cons
umption:  
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d not be generated to keep the state unchanged and save power consumption.
Quoted text here. Click to load it
the fact that the state does not change.  A flip flop that is clocked but d
oes not happen to change its output does not consume much power.  The power
 is needed to charge/discharge the loads that are being driven.  Any decrea
sed power consumption would have to do with the decrease in power in genera
ting the clock input to the flip flop.  But shifting from a common clock to
 adding a gate that generates a clock probably does not lower power since t
he same number of clock signals are being generated.  If the gated clock ro
uting is a higher capacitive route then when using a free-running clock the
n you can consume more power.  This is the result when trying to implement  
gated clocks in FPGA.  ASIC will be different.
Quoted text here. Click to load it
ion may not be necessary because too few state machines are implemented in  
any normal application.
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escribe in an FPGA results in an increase in power consumption.  I provided
 you with all of the details for your sample design.  The results of that a
nalysis are not "because too few state machines are implemented", it is bec
ause gated clocks in FPGA use more power, not less.  Again, that was with y
our sample design of that time which appears to be the same thing you are r
eusing here.
Quoted text here. Click to load it
VHDL as follows after the post is posted:
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e apparent usage of a possibly free running clock.
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ays it is.  No worries though, synthesis tools should optimize out the 'els
if' and leave the assignment 'WState <= WState_NS;' on every clock.  If t
he tool somehow leaves it in, then there will be an increase in power consu
mption due to use of additional logic required to implement 'elsif WState /
= WState_NS then'.  That increase would need to be counted against any po
wer savings that you think you're achieving.  Again, it would probably be w
orthwhile for you to do some analysis prior to posting and claiming...but a
fter all these years of not acting on this advice it doesn't appear that yo
u're willing to make that behavioral change.
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ecessary!
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nd claiming since the code is not complete and does not compile...as usual.
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do not find Hans of www.ht-lab.com giving his opinion. Usually his opinion  
is reasonable and informative and he knows many things outside the FPGA chi
ps beyond my knowledge.
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r earlier publication. The publication will happen about 14 weeks later sin
ce its filing date.
Quoted text here. Click to load it
to IEEE Transaction of circuits and System for publication. The review proc
ess may take up to 3 months.
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 cannot disclose any details about my invention until the transaction agree
s to publish my paper 3 months later or rejects my paper in 1 or 2 weeks.
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s almost the same as conventional method would generate, or maybe even simp
ler than conventional method.

I think you missed the mark by a wide margin on this one.  The logic needed
 for the clock gating is this...

elsif WState /= WState_NS then  

This is not so trivial compared to the FSM itself, especially in an ASIC.  
I would estimate it is approximately the same amount of logic in general.  
  


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 in state machines for the Cache II control. If they don't care about the p
ower saving or they have implemented some scheme in the implementation, my  
invention would be of few values, or otherwise it would be worth million of
 dollars.

For a patent to be valid it has to be non-obvious to a practitioner in the  
field.  I don't know how this is non-obvious to someone in the field of CPU
 design.  You may obtain a patent, but then lose a patent defense case in c
ourt.  But again, I didn't think cell phones would take off and now I have  
two.  


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out how to implement a state machine with clock gating function.  

What exactly is your "invention"???  Clock gating is nothing new.  It is ap
plied to many parts of a CPU.  Is your invention the idea of applying it to
 the individual FSMs in a CPU cache?  So if someone instead applies it to g
roupings of FSMs in a CPU cache they will have worked around your patent.
  


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gister and sell the application at http://www.ast.com/interested-in-selling
-to-ast/. I know the website because Google refers to the website and indic
ates they are a member of the site. I expect that Intel, IBM, AMD, Apple ma
y also be the members of the website. The site asks for the selling price d
uring registration. So it is important for me to assess my invention's valu
e properly.

What value have you assessed so far?  


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is website, not mention taking part in the discussion of my post.
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ore my registrations in the patent selling website.
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input for 8 registers in the block. Altera may be in the same situation. So
 clock enable is never a new thing and we don't have to pay attention to ho
w the clock trees work. For a CPU design, in my opinion, logic design and c
lock tree design are 2 separated domains one after another, and logic desig
ners never have to pay attention to the clock trees.  

Clock enable and clock gating are not the same thing.  Clock enable saves p
ower by not changing the FF state, but if the FF input is the same as the o
utput the state won't change anyway.  

Here is something to consider.  Clock gating saves power compared to clock  
enabling by reducing the power consumed in the clock tree.  How much of the
 clock tree will you actually be gating with a fine grained approach?  Cloc
k trees are exponential structures with a multiplier for the fan out at eac
h level.  With this fine grain approach you are only saving power in the fi
nal level and in fact, may be adding a level if your clock gating control i
s at a finer resolution than the last level of clock drive.  

Generally clock gating is used at a high level to gate the clock to section
s of a chip.  I expect it is seldom if ever used at a low level because the
 power saved is not optimal and the logic required is maximal.  

  Rick C.

  -- Get 6 months of free supercharging
  -- Tesla referral code - https://ts.la/richard11209

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
Am Samstag, 5. Januar 2019 05:30:08 UTC+1 schrieb Weng Tianxiang:
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ting function?
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ilog has the clock gating function for a state machine.

All languages support clock gating when explicit expressed and no language  
has an implicit statement for it.
This is as the clock is not really anything special in the language [1] and
 clock gating has several side effects that needs to be dealed with during  
layout. But in many cases you need to deal with some implications of clock  
gating during architectural design phase when writing the code.

[1] rising_edge(enable) or rising_edge(clock) have no difference for the la
nguage but very different results when using synthesis tools

bye Thomas

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