state machine with 2 clock's

Gray coding can deliver clockless state machines.

The big question you have to ask yourself is whether the 2 clocks can each want to transition the state machine to a different state within a few nanoseconds.

Do you want either clock to advance the machine? Do you want some states to transition with one clock and different states with the other clock?

You really have to get straight in your mind what your real needs are before you ask us to help you get it straight.

Gray coding is great for the glitchless decoding of counters, but it does not help in the more general case of a state machine (that is not just a counter). If the code change is more than just an increment or decrement, then multiple bits are likely to change, and the Gray decoding advantage is lost. Peter Alfke

My use of the term "Gray coding" for state machines refers the the general form of a number of states with specific coding (not one-hot) with 1 bit difference between any two state transitions. This does put strong constraints on the user to develop a scheme with the proper state coding and proper number of states to go through a sequence, change only one bit at a time, and return to the sequence with the proper state-bit coding. This was not intended to be confused with Gray code counters.

Peter, state machines can indeed be "Gray coded" but it is not the same as a Gray code counter. A more proper description might be a state machine that is designed so that all the state transitions have a hamming distance of 1, meaning that only one flip-flop changes state for each transition. Also, each state should only have one single bit decision variable in order for it to be reliable. This type of design is pretty much required for async (clockless) state machines. It is fairly easy to do for small simple machines, but can get very difficult as the number of branches in the machine increase. It often also requires some extra states so that any loops in the state machine can get close without any states that have more than one bit changing state.

We have done that, and "strong constraints on the user" is well put!. You can add dummy/extra states in many designs, to satisfy the One-Delta need, as many state paths are less time-critical. Normally a RESET is considered not needing to meet the One-Delta, tho you can arrange a dominant IDLE state to have a One-Delta reset.

For the OPs question, of two clocks, it may be possible to use a CLK and CLK_EN ?

-jg

I think this thread has served the purpose of being a dire warning against mixing unrelated clocks in one state machine. A naive design will inevitably get you in trouble. Really smart designers may be able to tip-toe through the tulips... Hats off to them! Peter Alfke