3 years ago
I think you missed the mark by a wide margin on this one. The logic needed for the clock gating is this...
elsif WState /= WState_NS then
This is not so trivial compared to the FSM itself, especially in an ASIC. I would estimate it is approximately the same amount of logic in general.
in state machines for the Cache II control. If they don't care about the p ower saving or they have implemented some scheme in the implementation, my invention would be of few values, or otherwise it would be worth million of dollars.
For a patent to be valid it has to be non-obvious to a practitioner in the field. I don't know how this is non-obvious to someone in the field of CPU design. You may obtain a patent, but then lose a patent defense case in c ourt. But again, I didn't think cell phones would take off and now I have two.
out how to implement a state machine with clock gating function.
What exactly is your "invention"??? Clock gating is nothing new. It is ap plied to many parts of a CPU. Is your invention the idea of applying it to the individual FSMs in a CPU cache? So if someone instead applies it to g roupings of FSMs in a CPU cache they will have worked around your patent.
gister and sell the application at -to-ast/. I know the website because Google refers to the website and indic ates they are a member of the site. I expect that Intel, IBM, AMD, Apple ma y also be the members of the website. The site asks for the selling price d uring registration. So it is important for me to assess my invention's valu e properly.
What value have you assessed so far?
is website, not mention taking part in the discussion of my post. ore my registrations in the patent selling website. input for 8 registers in the block. Altera may be in the same situation. So clock enable is never a new thing and we don't have to pay attention to ho w the clock trees work. For a CPU design, in my opinion, logic design and c lock tree design are 2 separated domains one after another, and logic desig ners never have to pay attention to the clock trees.
Clock enable and clock gating are not the same thing. Clock enable saves p ower by not changing the FF state, but if the FF input is the same as the o utput the state won't change anyway.
Here is something to consider. Clock gating saves power compared to clock enabling by reducing the power consumed in the clock tree. How much of the clock tree will you actually be gating with a fine grained approach? Cloc k trees are exponential structures with a multiplier for the fan out at eac h level. With this fine grain approach you are only saving power in the fi nal level and in fact, may be adding a level if your clock gating control i s at a finer resolution than the last level of clock drive.
Generally clock gating is used at a high level to gate the clock to section s of a chip. I expect it is seldom if ever used at a low level because the power saved is not optimal and the logic required is maximal.
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