I've got a Verilog function that I'd like to behave slightly differently depending on the value of a boolean argument, an argument whose value can be either (true) or (false). I tried:
module sid ();Then when I use Icarus to simulate it I get:function integer execOp; input integer left; input integer right; input boolean add; begin execOp = add ? left + right : left * right; end endfunction
endmodule
D:\Hf\Verilog\Unpacked\Common>\Icarus\bin\iverilog -g2009 -o sid.out sid.sv sid.sv:6: syntax error sid.sv:3: error: Syntax error defining function.Line 6 is the line where I declare variable (add). Is there a way to pass a boolean argument to a function, or am I going to have to declare an (enum) that has values (true) and (false)?D:\Hf\Verilog\Unpacked\Common>