I'm quite new to FPGA/Verilog and I'm not sure if this is the correct news group to use for this kind of posting - appologies if I've posted to the wrong place.
Anyway, I'm having problems using memory within a FSM. I'm currently using Xilinx ISE for a VirtexII. I'm trying to use the RAMB16_S18 memory primitive (SelectRAM).
I've written a short test which writes the sequence 0, 1, 2, 3 ....
14, 15 to the RAM in one state, then in another it reads it back. However, I read back the memory as 15, 0, 1, 2 .... 13, 14. I'm assuming that the 15 in the first read-back element is from the previous cycle and hence the whole lot is offset due to a clocking issue.I've truncated the code and copied below:
// Buffer clock for the ram wire Raw_Data_Profile_CLK; BUFG Raw_Data_Profile_CLK_Buffer(.I(Main_Clock), .O(Raw_Data_Profile_CLK));
// Setup the RAM reg [9:0] Data_Address; reg [15:0] Data_In; reg [2:0] Data_In_Parity; wire [15:0] Data_Out; wire [2:0] Data_Out_Parity; reg WE; RAMB16_S18 Data_RAM ( .DI( Data_In), .DIP( Data_In_Parity), .ADDR( Data_Address), .EN( 1'b1), .WE( WE), .SSR( 1'b0), .CLK( CLK), .DO( Data_Out), .DOP( Data_Out_Parity) );
// Update the Next State for the finite state machine reg [1:0] Current_State, Next_State; always @(posedge Main_Clock) begin Current_State