In my Verilog code I have this line:
reg [1:0] ip_list [0:3] = { 2'd2, 2'd1, 2'd0, 2'd1 };
Both Icarus and Vivado seem happy with it and it does what I expect.
However, I recently discovered Verilator and its lint capability so I've been running it over all my code to see if there is anything I ought to clean up. Verilator does not like this code, it says the LHS only has 2 bits while the right is 8 bits, so I'm wondering if I should be writing it differently. Maybe I've only been lucky so far that it's worked at all and I'd rather have my code correct than lucky.
Thanks for any help, Dave