Hi, Thank you for more people involved in this discussion.
Here is my prior art description of FIG. 1 on how a clock gating device is used. Clock gating device is used in my invention as a prior art device.
[0009] FIG. 1 is an interface diagram for any type of clock gating devi ce currently known in the art. These types of clock gating devices have the ir clock input ?>? coupled to a state machine?s clo ck source, with its clock pulse output C driving a clock pulse on the next cycle if the clock enable input E is asserted on the current cycle.
Because of the strict requirement of IEEE Transaction requirement on pap er's originality, I cannot disclose any details of my invention until about 3 months later. The paper contains 11 double column pages, excluding the a uthor's biography, and 10 related schematic diagrams of related state machi ne's circuits.
From the schematic diagrams you can immediately know that the full circuit of a state machine is much simpler than any counterpart of a conventional s tate machine circuit with clock enable logic naturally generated without an y extra logic.
t of a state machine is much simpler than any counterpart of a conventional state machine circuit with clock enable logic naturally generated without any extra logic.
The schematic of a ripple counter implemented with T flip flops is also qui te simple when compared to that of a conventional synchronous counter. As I previously posted, use of T flip flops rather than D flip flops (and the consequential generation of gated clocks to support synthesis using T flip flops) is existing prior art that is covered in old textbooks. Your chosen subset of use cases such as state machines is a restriction over what is a lready out as prior art which covered all synchronous machines.
?Your chosen subset of use cases such as state machines is a rest riction over what is already out as prior art which covered all synchronous machines. ?
My method only applies to a state machine circuit and defines many brand ne w concepts for a state machine.
The method is useless for FPGA as nobody cares about a low power state mach ine circuit. The saver of my invention is the case of CPU' 100,000 state ma chines for 6M L2 cache.
Sigh, can't believe I keep letting myself get dragged into these discussions...
Weng - what you're completely missing what many have been telling you - your definition of a "state machine" is so broad that it's essentially meaningless. Since you think that YOUR definition of a "state machine" includes this 6M L2 cache, then as Ken and I have tried to tell you, your "state machine" definition includes the subset of ALL synchronous machines.
This isn't a terrible definition of a state machine, (but one that doesn't offer much utility). But this just goes to show you that any Super Snazzy Ideas you've got have already been shown in prior art, in the general set of all synchronous machines, as Ken's trying to communicate to you.
I fear you'll ignore this information as you've ignored most of what information others have tried to communicate to your in the past (in this thread and others). But I'm saying it anyway.
I'll await your reply with more sets of patent result hits from google... ;)
Here is the definition of a state machine introduced in my prior art part:
[0003] Traditionally a deterministic finite state machine is mathematica lly defined as a set of 6-tuple M = (?, ?, Q, q0, ?, ? ?), where ? is a finite set of input symbols, ? /= 0 is a fin ite set of output symbols, Q /= 0 is a finite set of states, q0 ? Q is the ?reset? state, ?(q, a) : Q x ? ? Q is the transfer function, and ?(q, a) : Q x ? ? ? i s the output function. [0004] Conventional state machine theory has following State Machine Axi om: [0005] State Machine Axiom A state machine has one and only one state being active on any cycle after the state machine is properly initialized.
"This definition matches all synchronous digital circuits."
Do you plan to retrieve the following claiming?
"Weng - what you're completely missing what many have been telling you - your definition of a "state machine" is so broad that it's essentially meaningless."
list only the search word "L2 cache inassignee:intel" and you can find thro ugh Google there are 4,830 patents filed and issued by Intel, the search wo rd "L2 cache state machine inassignee:intel" and it leads to 4,360, each of them is related to a type of state machines.
it designer if he does not seriously consider or design a state machine.
and Altera. Reading Xilinx and Altera' patents gives me the knowledge on ho w they design their FPGA chips. Reading Intel, IBM and AMD' patents gives m e the knowledge on how they design something very complex and new technolog y trend. And through the reading I find many topics for me to further devel op.
into low power mode in response to special bus cycles executed on the bus"
ne
wer power status, no matter what type of state machines is, and the logic r esource usage is less than a conventional synthesizer would generate.
I would estimate it is approximately the same amount of logic in general. "
n "WState /= WState_NS". Is it obvious to you?
If you can perform an equality comparison without using gates, that will be of tremendous value in logic design. Instead of using conventional gates all logic can be decomposed to an expression using equality comparisons (th e equivalent of the XOR applied to bits followed by an OR gate). So if you can perform the not equal comparison on a multi-bit word without gates, th en every digital logic design can be implemented with no logic gates at all !
By all means patent that and the world will beat a path to your door!!!
But obviously what you said is not true. So I must be misunderstanding you .
Perhaps you can explain what you really mean.
Rick C.
-+ Get 6 months of free supercharging -+ Tesla referral code -
First of all, I have to appreciate your following guessing: "If you can perform an equality comparison without using gates, that will b e of tremendous value in logic design. Instead of using conventional gates all logic can be decomposed to an expression using equality comparisons (t he equivalent of the XOR applied to bits followed by an OR gate). So if yo u can perform the not equal comparison on a multi-bit word without gates, t hen every digital logic design can be implemented with no logic gates at al l! "
But You are wrong in guessing my invention without any logic bases.
There is no comparison at all.
I use another trick to avoid any comparison for a state machine circuit and reach a conclusion that you need comparison to achieve.
The trick seems to be non-obvious to you now.
But don't worry, your conclusion is wrong too: "obviously what you said is not true. So I must be misunderstanding you."
Do you mean will I retract my statement? No I won't because it's consistent. The definition you listed in the grandparent post of a "state machine" has such a broad scope that EVERY synchronous digital circuit in existance fits the definition.
You can prove me wrong by counter-example. I assert that your definition of "state machine" is so broad that any synchronous digital circuit will match your definition. If you can show/explain ANY synchronous digital circuit that does NOT match your definition of a "state machine" you'll have falsified my assertion.
I can come at it from the opposite end and suggest a few example of synchronous digital circuits that one normally wouldn't think of as "state machines" but fit your definition none-the-less.
But I think the excercise (of trying to come up with a counter-example) would help you understand what we've been trying to communicate to you.
Perhaps Rick is wrong as you state (or maybe not), but I am not. You have disclosed enough to discern what you think is the important idea to patent (although I don't pretend to know all that you may claim from that idea). S ince you cannot disclose until you hear about publication, I won't disclose either.
t and reach a conclusion that you need comparison to achieve.
But in fact the 'trick' as you call it is obvious and also, unfortunately f or you, the idea is in fact old prior art that you are simply not recognizi ng. But maybe the PTO won't pick up on it, or maybe you'll find someone to part with $$ for what you will be marketing as a 'new' idea or maybe, if th e patent is granted, you'll get challenged in court and lose. Time, as they say, will tell.
ically defined as a set of 6-tuple M = (?, ?, Q, q0, ?, ?), where ? is a finite
/= 0 is a finite set of states, q0 ? Q is the ?reset? ? state, ?(q, a) : Q x ? ? Q
is the output function.
Axiom:
te being active on any cycle after the state machine is properly initialize d.
Yes, that's true. A FSM could be a dedicated statemachine written in one HD L module, but each counter is a simple FSM and each complete logic design c an be seen as a statemachine.
Every part of a statemachine containing at least 2 states and 1 input and o utput is itself a statemachine and every combination of 2 statemachines is one statemachine. FSM is just a model to describe a digital circuit with at least one sequential element.
Perhaps some would call ANY synchronous digital circuit a state-machine, but the more classical definition would imply that it be a system with a single clock domain as it is the transformation from one 'State' to another 'State' on *The* clock edge, with the definition of the Next State being a function of the Previous State and the Inputs. The concept of previous and next imply a singular concept of time steps, thus a single clock domain (though clock gating/enables of that domain would be allowed).
A system using multiple, not tightly related clocks, would fail that definition, and in the FSM view of the world would be multiple intertwined State Machines. Most digital system can be viewed as a set of coupled FSMs based on the number of clock domains in the system. Poly-Phase systems and system using wave phasing (multiple clocks between registers) stretch the concept of a State Machine a bit, but can probably be reasonably described as such. Some systems with Asynchronous bits can get harder to describe as a FSM.
Yes, exactly. The qualification of a single clock - or as you note - related clocks is what I was trying to cover with the term SYNCHNRONOUS digitial circuits. In one of my post up the thread I mentioned a single clock - Kevin more correctly labeled the requirements as SYNCHRONOUS which I think summarizes the requirements better so I took that label.
I'll say again, any SYNCHRONOUS digital circuit meets Weng's definition of a state machine.
Sorry, I'm not going to prior art research for your patent application for you.
However, I will suggest that you tend to take a very narrow view of some topic, such as a state machine, and appear to ignore applicable work that is more general, of which your 'state machine' is simply a subset.
Any marginally competent cache designer understands that only one cache lin e is accessed at a time. So the cache is designed as a RAM with data, tags, and state. Each cycle the data, tags and state are read, and a single stat e machine is used to generate the next state, which is written back into th e RAM.
There are plenty of papers > Hi Mark,
PU
t:
PU;
or instructions in coherence. I will not be surprised that each L2 cache li ne may have up to 8 state machines to control its working.
or instructions in coherence. I will not be surprised that each L2 cache li ne may have up to 8 state machines to control its working.
or instructions in coherence. I will not be surprised that each L2 cache li ne may have up to 8 state machines to control its working.
or instructions in coherence. I will not be surprised that each L2 cache li ne may have up to 8 state machines to control its working.
or instructions in coherence. I will not be surprised that each L2 cache li ne may have up to 8 state machines to control its working.
be of tremendous value in logic design. Instead of using conventional gat es all logic can be decomposed to an expression using equality comparisons (the equivalent of the XOR applied to bits followed by an OR gate). So if you can perform the not equal comparison on a multi-bit word without gates, then every digital logic design can be implemented with no logic gates at all! "
t and reach a conclusion that you need comparison to achieve.
"
Ok, I am reading your code. So you are saying your code is not what you me an. Got it.
Rick C.
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ine is accessed at a time. So the cache is designed as a RAM with data, tag s, and state. Each cycle the data, tags and state are read, and a single st ate machine is used to generate the next state, which is written back into the RAM.
ew data is different from the present state, and uses that to generate a cl ock pulse only if necessary.
Congratulation!
Your post is the best and most valuable post in this thread!
Invincible! Marvelous! Smartest!
Your post makes me shameful and speechless!
Hope you join my later post.
I will continue to pursue my next sets of inventions!
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