Is it possible to have a parameterized verilog module name in verilog or systemverilog?

Question

Hi,

I am trying create verilog module that can support parameterized instance n ame. I understand that the signal width and other such things can be parame terized. But can we also parameterize the module instance name?

In following code, I am curious if there is any way SomeDynamicInstanceName can be parameterized also? I can try to use system verilog if that can hel p here

My purpose is to be able to reuse the verilog gmon module (generic verilog module) for various types of signals. But for a reason, I need to change t he SomeDynamicInstanceName. I have control of a verilog file where I insta ntiate gmon verilog module so I can pass the parameters.

Prompt response is greatly appreciated.

`timescale 1 ns/100 ps

module gmon #( parameter WIDTH = 32 ) (Clk, Rst, SignalName);

// PCIE MST_BIF input Clk; input Rst; input [WIDTH-1:0] SignalName;

// input [31:0] SignalName_ret

reg [WIDTH-1:0] SignalName_d1; //reg [31:0] SignalName_d2;

always @ (posedge Clk) begin SignalName_d1

glen herrmannsfeldt · Accepted Answer

(snip)

I didn't figure out from the example, so maybe you can explain again.

I mostly don't use parameters, but often enough generate a new instance with a new name.

I might have an eight bit register named reg8, and a 16 bit one named reg16, where others might name it reg with a parameter that is 8 or 16.

But it is one or the other, not both.

Well, I suppose one way to implement reg8 and reg16 is though instantiating reg with parameter 8 or 16, but another way is to use a program in some other language to generate source modules as appropriate.

It is very easy, for example, with awk to generate appropriate modules with appropriate names.

-- glen

Kevin Neilson · Answer

I'd say your options are pretty limited.

Use a precompiler directive, which you can set when calling the synthesizer or simulator: test_module #(.FIFOBUF_WIDTH(WIDTH)) `DynamicInstanceName ( ...

Use a generate-case to select between a few instance name options based on a parameter.
Like the other respondent said, use Awk or TCL or some other scripting language to modify or write out HDL before running synth/sim. You could probably just put the name into an include file and then include that: test_module #(.FIFOBUF_WIDTH(WIDTH)) `inclue "Instancename.txt" ( ...

These are all a bit kludgey.

-Kevin

Kevin Neilson · Answer

/sim. You could probably just put the name into an include file and then include that:

I meant "include".

You can even use Verilog to generate Verilog. Pretty kludgey, but I've done that. You have to run the Verilog-generating Verilog first. Better to use some other language.

Kevin Neilson · Answer

I don't know how much control you need, but I was thinking, for option #2, you could control at least the numeric index of the name, I think.  For example: parameter K = 4; generate for (genvar j=K; j

Brad Whitlock · Answer

name. I understand that the signal width and other such things can be para meterized. But can we also parameterize the module instance name?

me can be parameterized also? I can try to use system verilog if that can h elp here

g module) for various types of signals. But for a reason, I need to change the SomeDynamicInstanceName. I have control of a verilog file where I ins tantiate gmon verilog module so I can pass the parameters.

Take a look at Verilog-mode (AUTO) for Emacs, if you use Emacs. You wont ge t dynamic instance names with AUTO, but it is easy to do special things per instance via AUTO_TEMPLATEs. Like if instance name is 'gmon0' connect bit n to input y. If instance name is 'gmon1' then connect bit n+1 to input y e tc. This could offer a new path to solve your issue.

Jan Coombs · Answer

There is a trivial example here:    search page for    Professional Code - with test bench  Notice that there is no width parameter nor global to indicate how wide Multibit_Adder should be.  Jan Coombs --  email valid, else fix dots and hyphen jan4clf2014@murrayhyphenmicroftdotcodotuk

Is it possible to have a parameterized verilog module name in verilog or systemverilog?

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