BITSLIP STATE MACHINE

Hi,
I am trying to design a state machine for bitslip function but simulations dont seem to be correct. I cant figure out where the bug is.
here is the code and test bench.
module bitsliplogic(
CLOCK,
RESET,
DATAIN,
SYNC_PATTERN,
BITSLIP,
BITSLIP_DONE
);

parameter data_width = 10;
parameter counter_width_0 = 16;
parameter DELAY_0 = 10; //10 clock cycle
input CLOCK;
input RESET;
input [data_width-1:0] DATAIN;
input [data_width-1:0] SYNC_PATTERN;
output BITSLIP;
output BITSLIP_DONE;
//State Machine
parameter IDLE = 7'b0000001;
parameter CHECK_SYNC = 7'b0000010;
parameter ASSERT_BITSLIP = 7'b0000100;
parameter WAIT_0 = 7'b0001000;
parameter DEASSERT_BITSLIP = 7'b0010000;
parameter BITSLIP_SEQ_DONE = 7'b0100000;
///////////////////////////////////////////////////////////////////////////////////////////////////////////
reg [counter_width_0 - 1:0] counter_0;
reg [6:0] state, next;
//register for State Machine
reg bitslip_sig;
reg bitslip_reg;
reg bitslip_done_reg;
reg start_count;
reg [counter_width_0-1:0] count_val;
wire count_done;
///////////////////////////////////////////////////////////////////////////////////////////////////////////
assign count_done = (counter_0 == count_val)? 1'b1 : 1'b0;
//assignment for output
assign BITSLIP = bitslip_reg;
assign BITSLIP_DONE = bitslip_done_reg;
///////////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge CLOCK or posedge RESET)
if (RESET)
counter_0
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atifnawaz08
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