Clock Gating !!!

Hi All,

I m facing some problems with clock gating in Virtex II FPGA using BUFGMUX, The Xilinx ISE 6.2.03i is saying the design is not completely routable. I know that clock gating in an FPGA is not advisable, but my requirement is like that. I have total 15 clocks of 5 diffterent frequencies. All these 15 clocks are gated with gate enable before going to the individual modules. The gating must be done in my clock tree module only.

Can anyone please give some inputs on this... Any help will be greatly appreciated.

Thanks... Chandrasekhar.

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I assume you have gated clock because you want to suspend the operation of some sequential logics when you want it. If that's what you want, instead of having gated clock, you can have "clock enable". The following example explains what I mean by "clock enable"

Let's say you want to have a 4 bit counter, but you want to stop the counter from counting when you want it. You can do it this way always @(posedge clk) begin if (clock_enable) counter

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The second example should be:

reg [1:0]clock_enable; always @(posedge clk) begin clock_enable

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No it isn't. Use enables instead. The tool has saved you from months of pain by refusing to connect up such an abomination!

Fix it so you have one clock. Make it faster than the others; why not use a DCM to create it? Use enables for your original 15 clocks. If necessary, retime the stuff from the various clock domains on the way in, and on the way out, in your 'clock tree module'. A little thought up front will save you so many problems. Here's a resynchronising circuit posted by Rick Collins to get you going.

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Good luck, Syms.

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SynplifyPro has an option to automatically convert gated clocks into clock enables. Very useful for ASIC prototyping.

Cheers, Jon

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