I m facing some problems with clock gating in Virtex II FPGA using BUFGMUX, The Xilinx ISE 6.2.03i is saying the design is not completely routable. I know that clock gating in an FPGA is not advisable, but my requirement is like that. I have total 15 clocks of 5 diffterent frequencies. All these 15 clocks are gated with gate enable before going to the individual modules. The gating must be done in my clock tree module only.
Can anyone please give some inputs on this... Any help will be greatly appreciated.