Latest threads in Field-Programmable Gate Arraysshow only best voted threads
| Subject | Author | Posted | Replies | |
|---|---|---|---|---|
|
|
Xst_Choice nodes
Hey, Im trying some synthesis with Xilinx Xst in ISE 9.2 and i'm getting this error ERROR:Xst:2259 - Unit has internal Xst_Choice nodes Anyone know what an Xst_Choice node is? I've no idea what it is...
1
|
16 years ago
|
1 | |
|
|
"Number of BSCANs: 2 out of 1 200%"
Hi, I have added Chipscope to my design, but it seems to be incompatible because of BSCANS: Number of BSCANs: 2 out of 1 200% (OVERMAPPED). The reason is that I need to use OPB_MDM since I have to...
6
|
16 years ago
|
6 | |
|
|
coregenerator bram in synplify pro error
I am trying to get rams in xilinx to synthesize in synplify pro. I am a novice in syplify pro. I used the core generator to generate BRAM and then since for brams we cannot generate edif files I used...
11
|
16 years ago
|
11 | |
|
|
Why does ISE 9.2 optimize out the logic
Hi, I want to use RLOC function of ISE 9.2. I find at the end, all logic are optimized out, see below the simplest example. I can see the results after synthesis are correct. How to avoid this? Thanks...
—
|
16 years ago
|
— | |
|
|
now I can talk about it...
Ta Da! Austin
14
|
16 years ago
|
14 | |
|
|
ISE 9.2i project question
When i add existing source files ISE copies them to the project directory but i want to use them in their current directories (by reference). It's a small point but i cant seem to find out how to do...
1
|
16 years ago
|
1 | |
|
|
Simple (?) timing constraint for output pins
Hi *, I am driving a bunch of DACs each having its own SPI bus with a Virtex4 FPGA. The test design is up and running fine (generating a sine output via an DDC generator implemented on the fabric)....
6
|
16 years ago
|
6 | |
|
|
Xilinx and Modelsim?
Hi, please forgive me for any ignorance in this question, but I am really lost. I have tried to get Xilinx ISE Webpack 9.2i to work with modelsim. But it just doesn't seem to work. Now I am not very...
6
|
16 years ago
|
6 | |
|
|
Partial reconfiguration by using ICAP
Dear all: My target board is the Xilinx ML310, which contains a Virtex-II Pro XC2VP30 FPGA. I followed the EAPR flow and successfuly generated my partial bitstreams. My system architecture was created...
—
|
16 years ago
|
— | |
|
|
Impact won't program XC3S200, does program XC3SD1800A
Hi everyone, My setup: ISE10.1 webpack, Digilent Spartan 3 kit, ExtremeDSP 1800A kit, Digilent parallel JTAG cable, Ubuntu 7.10. With xc3sprog I can write my configuration files to the Spartan-3 kit....
2
|
16 years ago
|
2 | |
|
|
JTAG: First of 4 Spartan-3E always UNKNOWN
Hi All, I have custom board with 4 Spartan-3E (XC3S500E-PQ208). For configuration I have both JTAG and slave serial access. Slave serial works fine. However, when I try to identify the JTAG chain the...
12
|
16 years ago
|
12 | |
|
|
Welcome to our world - Blog
Yeah! Peter and I (and Ken) have a new outlet. Just getting started, so please stop by, check it out, and give us some helpful feedback (before we lose the developers, and are unable to change stuff...
—
|
16 years ago
|
— | |
|
|
ISE 64 bit
Are there any plans to offer an ISE WebPack version that can run under Vista 64 bit ? TIA, Rog.
—
|
16 years ago
|
— | |
|
|
increase memory of microblaze
hi, is it possible to increase the available memory for a microblaze after it has been created ? .. i have created a microblaze with 16kb blockram using the base system builder, but now i want to use...
3
|
16 years ago
|
3 | |
|
|
Using USB programming cables from Xilinx and Lattice on one Windows machine
Hey *, I'm trying to use USB programming cables from both Xilinx and Lattice on the same Windows machine. No luck so far, I can only get one of them working at a time, when I completely uninstall the...
6
|
16 years ago
|
6 |