Field-Programmable Gate Arrays

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NoisII or else.

Hi, Simple question. Can I put a NiosII on an FPGA alone, no ROM no DRAM no SRAM no nothing, Just the FPGA ? (examples...
8 comments posted 18yrs
posted by cupidoREMOVE
8 comments posted 18yrs posted by cupidoREMOVE

OBUF gate delay

Hi, I am using virtex4 device for my designs. In timing analysis i found OBUF in V4 is 3.79ns which is a big obstacle f...
3 comments posted 18yrs
posted by jamicrotech
3 comments posted 18yrs posted by jamicrotech

MIG/Corgen to XPS core insertion

Hello all, I am creating at MIG a external DDR2 Memory controller. Then i am trying to add this core to an XPS design....
3 comments posted 18yrs
posted by lastval
3 comments posted 18yrs posted by lastval

Avalon Bus <-> Wishbone Bus

I'm pretty new to fpgas, but theres an i2c core on opencores.org that I'd like to use in my Altera project. I understan...
3 comments posted 18yrs
posted by benn686
3 comments posted 18yrs posted by benn686

Modify POF with new ESB (ROM) content?

Hello, We have a design that has an embedded PIC processor that uses ESB's for instruction and data RAM. The target is...
9 comments posted 18yrs
posted by jshamlet
9 comments posted 18yrs posted by jshamlet

FPGA configuration mode on ML310

Hi! everyone I have a very basic problem. I know that the 6-position DIP switch on the ML403 board can control the conf...
4 comments posted 18yrs
posted by grant0920
4 comments posted 18yrs posted by grant0920

Xilinx xilfatfs and systemACE speed issue

Hi I am trying to squeeze some read speed out from CF using systemACE and xilinx standard libraries, but the performanc...
4 comments posted 18yrs
posted by Antti.Lukats
4 comments posted 18yrs posted by Antti.Lukats

system level language: why all this fuss about

why all this fuss about the need for new system level languages and higher abstraction...systems were also heterogeneou...
9 comments posted 18yrs
posted by karl.polytech
9 comments posted 18yrs posted by karl.polytech

problem with synthesis of a state machine

The following code runs well in simulation mode but synthesis fails. Please let me know how I can get this synthesized,...
5 comments posted 18yrs
posted by fei.liu
5 comments posted 18yrs posted by fei.liu

PLA datasheet - PLS161

Hi all, I am looking for the datasheet of the PLS161 which was a PLA. My interest in it is purely academic. I am teachi...
2 comments posted 18yrs
posted by jozamm
2 comments posted 18yrs posted by jozamm

Project Ideas

Hello everyone i have been working on FPGA and CPLD's for the past 6 months and i have gained sufficent expertise to do...
1 comments posted 18yrs
posted by ankitanand1986
1 comments posted 18yrs posted by ankitanand1986

Xilinx inferred FIFOs

What is the current status now about inferring FIFOs in Virtex 4 or 5 with VHDL ? Brad Smallridge Ai Vision
9 comments posted 18yrs
posted by bradsmallridge
9 comments posted 18yrs posted by bradsmallridge

UK Embedded Masterclass

Hi, just a quick note to let you know that we are running another Embedded Masterclass - it is in London and but to be...
0 comments posted 18yrs
posted by richard
0 comments posted 18yrs posted by richard