Field-Programmable Gate Arrays

coregenerator bram in synplify pro error

I am trying to get rams in xilinx to synthesize in synplify pro. I am a novice in syplify pro. I used the core generato...

11 comments posted 18yrs

posted by nbg2006

11 comments posted 18yrs posted by nbg2006

Why does ISE 9.2 optimize out the logic

Hi, I want to use RLOC function of ISE 9.2. I find at the end, all logic are optimized out, see below the simplest exam...

0 comments posted 18yrs

posted by rxjwg98

0 comments posted 18yrs posted by rxjwg98

now I can talk about it...

http://biz.yahoo.com/prnews/080331/aqm029a.html?.v=7 Ta Da! Austin

14 comments posted 18yrs

posted by austin

14 comments posted 18yrs posted by austin

ISE 9.2i project question

When i add existing source files ISE copies them to the project directory but i want to use them in their current direc...

1 comments posted 18yrs

posted by robquigley

1 comments posted 18yrs posted by robquigley

Simple (?) timing constraint for output pins

Hi *, I am driving a bunch of DACs each having its own SPI bus with a Virtex4 FPGA. The test design is up and running f...

6 comments posted 18yrs

posted by t.landschoff

6 comments posted 18yrs posted by t.landschoff

Xilinx and Modelsim?

Hi, please forgive me for any ignorance in this question, but I am really lost. I have tried to get Xilinx ISE Webpack...

6 comments posted 18yrs

posted by sunnzy

6 comments posted 18yrs posted by sunnzy

Partial reconfiguration by using ICAP

Dear all: My target board is the Xilinx ML310, which contains a Virtex-II Pro XC2VP30 FPGA. I followed the EAPR flow an...

0 comments posted 18yrs

posted by grant0920

0 comments posted 18yrs posted by grant0920

Impact won't program XC3S200, does program XC3SD1800A

Hi everyone, My setup: ISE10.1 webpack, Digilent Spartan 3 kit, ExtremeDSP 1800A kit, Digilent parallel JTAG cable, Ubu...

2 comments posted 18yrs

posted by boven

2 comments posted 18yrs posted by boven

JTAG: First of 4 Spartan-3E always UNKNOWN

Hi All, I have custom board with 4 Spartan-3E (XC3S500E-PQ208). For configuration I have both JTAG and slave serial acc...

12 comments posted 18yrs

posted by ajg112

12 comments posted 18yrs posted by ajg112

Welcome to our world - Blog

http://forums.xilinx.com/xlnx/blog/article?message.uid=7994 Yeah! Peter and I (and Ken) have a new outlet. Just getting...

0 comments posted 18yrs

posted by austin

0 comments posted 18yrs posted by austin

ISE 64 bit

Are there any plans to offer an ISE WebPack version that can run under Vista 64 bit ? TIA, Rog.

0 comments posted 18yrs

posted by rogerwilson

0 comments posted 18yrs posted by rogerwilson

increase memory of microblaze

hi, is it possible to increase the available memory for a microblaze after it has been created ? .. i have created a mi...

3 comments posted 18yrs

posted by kislo02

3 comments posted 18yrs posted by kislo02

Using USB programming cables from Xilinx and Lattice on one Windows machine

Hey *, I'm trying to use USB programming cables from both Xilinx and Lattice on the same Windows machine. No luck so fa...

6 comments posted 18yrs

posted by news_mar08

6 comments posted 18yrs posted by news_mar08

Writing to DDR RAM on Virtex II Pro Board on PLB Bus

My question: How can I write to DDR SDRAM from a custom IP core on the PLB Bus? Background: I am developing a custom IP...

2 comments posted 18yrs

posted by admbarnett

2 comments posted 18yrs posted by admbarnett

fpga reset (re-initialize) of spartan3e

Hi, is it possible to force a re initialization from within the fpga ? if I have, for instance. transfered new configur...

3 comments posted 18yrs

posted by kislo02

3 comments posted 18yrs posted by kislo02