Field-Programmable Gate Arrays

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Xst_Choice nodes

Hey, Im trying some synthesis with Xilinx Xst in ISE 9.2 and i'm getting this error ERROR:Xst:2259 - Unit has internal...
1 comments posted 18yrs
posted by robquigley
1 comments posted 18yrs posted by robquigley

"Number of BSCANs: 2 out of 1 200%"

Hi, I have added Chipscope to my design, but it seems to be incompatible because of BSCANS: Number of BSCANs: 2 out of...
6 comments posted 18yrs
posted by pbantunez
6 comments posted 18yrs posted by pbantunez

coregenerator bram in synplify pro error

I am trying to get rams in xilinx to synthesize in synplify pro. I am a novice in syplify pro. I used the core generato...
11 comments posted 18yrs
posted by nbg2006
11 comments posted 18yrs posted by nbg2006

Why does ISE 9.2 optimize out the logic

Hi, I want to use RLOC function of ISE 9.2. I find at the end, all logic are optimized out, see below the simplest exam...
0 comments posted 18yrs
posted by rxjwg98
0 comments posted 18yrs posted by rxjwg98

now I can talk about it...

http://biz.yahoo.com/prnews/080331/aqm029a.html?.v=7 Ta Da! Austin
14 comments posted 18yrs
posted by austin
14 comments posted 18yrs posted by austin

ISE 9.2i project question

When i add existing source files ISE copies them to the project directory but i want to use them in their current direc...
1 comments posted 18yrs
posted by robquigley
1 comments posted 18yrs posted by robquigley

Simple (?) timing constraint for output pins

Hi *, I am driving a bunch of DACs each having its own SPI bus with a Virtex4 FPGA. The test design is up and running f...
6 comments posted 18yrs
posted by t.landschoff
6 comments posted 18yrs posted by t.landschoff

Xilinx and Modelsim?

Hi, please forgive me for any ignorance in this question, but I am really lost. I have tried to get Xilinx ISE Webpack...
6 comments posted 18yrs
posted by sunnzy
6 comments posted 18yrs posted by sunnzy

Partial reconfiguration by using ICAP

Dear all: My target board is the Xilinx ML310, which contains a Virtex-II Pro XC2VP30 FPGA. I followed the EAPR flow an...
0 comments posted 18yrs
posted by grant0920
0 comments posted 18yrs posted by grant0920

JTAG: First of 4 Spartan-3E always UNKNOWN

Hi All, I have custom board with 4 Spartan-3E (XC3S500E-PQ208). For configuration I have both JTAG and slave serial acc...
12 comments posted 18yrs
posted by ajg112
12 comments posted 18yrs posted by ajg112

Welcome to our world - Blog

http://forums.xilinx.com/xlnx/blog/article?message.uid=7994 Yeah! Peter and I (and Ken) have a new outlet. Just getting...
0 comments posted 18yrs
posted by austin
0 comments posted 18yrs posted by austin

ISE 64 bit

Are there any plans to offer an ISE WebPack version that can run under Vista 64 bit ? TIA, Rog.
0 comments posted 18yrs
posted by rogerwilson
0 comments posted 18yrs posted by rogerwilson

increase memory of microblaze

hi, is it possible to increase the available memory for a microblaze after it has been created ? .. i have created a mi...
3 comments posted 18yrs
posted by kislo02
3 comments posted 18yrs posted by kislo02