Why does ISE 9.2 optimize out the logic

Hi, I want to use RLOC function of ISE 9.2. I find at the end, all logic are optimized out, see below the simplest example. I can see the results after synthesis are correct. How to avoid this? Thanks in advance.

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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library UNISIM; use UNISIM.VComponents.all;

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