JTAG: First of 4 Spartan-3E always UNKNOWN

schematics:

impact select chain debug issue TLR

create a string of 128 '11111111111111111.. with some text editor, paste it into edit box for dr shift shift it out you should see JTAG ID of all 4 devices in chain scaned back in

if there is 32 bit 1'1 at one end of the return string your chain is broken

Antti

Antti wrote: > impact select chain debug

Here is the output (Cut and paste from the impact log) for this operation done 4 times. You can see how the output is slightly different each time, but the changes are only within the first 32 bits (i.e. the first device)

// *** BATCH CMD : bsdebug -scandr

11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111

TDO Capture Data:

11110000011000000010000010010011000000011100001000100000100100110000000111000010001000001001001100000001110000100010000010010011

// *** BATCH CMD : bsdebug -scandr

11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111

TDO Capture Data:

11110000000110001001000001000011000000011100001000100000100100110000000111000010001000001001001100000001110000100010000010010011

// *** BATCH CMD : bsdebug -scandr

11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111

TDO Capture Data:

11100000001110000100010000100001000000011100001000100000100100110000000111000010001000001001001100000001110000100010000010010011

// *** BATCH CMD : bsdebug -scandr

11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111

TDO Capture Data:

11000000011100001000100001001011000000011100001000100000100100110000000111000010001000001001001100000001110000100010000010010011

1=AD11111111111111111111111111111111111111111111111111111 0=AD00010001000001001001100000001110000100010000010010011 1=AD11111111111111111111111111111111111111111111111111111 0=AD00010001000001001001100000001110000100010000010010011 1=AD11111111111111111111111111111111111111111111111111111 0=AD00010001000001001001100000001110000100010000010010011 1=AD11111111111111111111111111111111111111111111111111111 0=AD00010001000001001001100000001110000100010000010010011

hm chain aint completly broken, weird well i have seen wrong jtag id been returned, it was digged down to have excessive 100mhz noise on VCCINT

Antti

Looks like I've got a similar problem. After removing the oscillator module the JTAG identification works fine.

Thanks for the pointer

Andy

How did you resolve the 100mhz noise source problem..?

removing the 100mhz oscillator :) that PCB proto was SO BAD that no powersupply bypassing helped.. i tried and looked with the scope

BTW it was weird, i was also using lab power supply, so while sweeping the VCC i could see the JTAG ID to change from virtex to spartan and then failing completly

Antti

I've dropped in a lower frequency oscillator module, that seems to have improved things. It's not a massive problem, I'll just use a DCM to multiply things up.

I'm guessing the oscillator was causing noise on VCCO. However, isn't the JTAG TAP and IO powered by VCCAUX?

Andy

Andrew

I would be interested to know if now that JTAG works you hit the same "feature" that we did recently (otherwise we have a hidden design bug).

If you power up and program any device using JTAG it completes programming, releases DONE but sees that DONE is still held by the other three FPGAs and decides that it has failed and IMPACT returns failed. We have to try to program all the devices which will all fail except the last one which releases DONE and sees it high and so passes. The other three then need programming again which will pass as done is high.

Colin

schematics:

Try to add 100R serial resitor between each TCK and the corresponding FPGA PAD (up the PAD pin and add the resistor) Verify that the last TDO (FPGA3config to your JTAG connector) is not routed close to the TCK !!!

I am almost sure your VCCAUX is OK, I will first check the JTAG signal integrity ;-)

Also, check that the GND is weel connected between the board and your JTAG emulator.

- Larry

SOmehow JTAG is extremely sensitive to electrical parameters. IIRC the method used to generate the waveforms by Impact is not the best around (data and clk are changed simultaneously). I've also had these sort of problems on boards with multiple FPGAs. Sometimes adding a small RC to the clock (TCK) line may help. You can use an oscilloscope to very setup & hold timing on the JTAG bus.

--
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E-mail naar nico@nctdevpuntnl (punt=.)

Didn't that defeat the purpose of the pcb ..? :)

So a new pcb was made..?, what was explicitly changed..?

sweeping Vcc?, iee overlaying a variable amplitude and frequency signal onto Vcc?

By the way.. is switch regualator ripple a big issue for spartan fpga?

That's interesting. I did wonder how the JTAG bus is driven. I've had a small project running in the background for a while to make my own usb JTAG module. Perhaps it's time to finish it off.

Andy