Atmel AVR32 user guide: SATS – Saturate Signed

AVR32

SATRNDU – Saturate with Rounding Unsigned

Description This instruction considers the value in (Rd>>sa)[bp-1:0] as a unsigned value. Rounding is performed after the shift. If the value in (Rd>>sa)[31:bp] is not merely a zero extentation of this value, overflow has occurred and saturation is performed to the maximum unsigned positive value or zero. If saturation occurs, the Q flag is set. An arithmetic shift is performed on Rd. If bp equals zero, no saturation is performed.

Operation:

I. Temp \leftarrow Rd >> sa if (sa != 0) Rnd = Rd[sa-1] Temp = Temp + Rnd; If ((Temp == ZE( Temp[bp-1:0])) || (bp == 0) ) Rd \leftarrow Temp; else if (Temp[31] == 1) Rd \leftarrow 0x0000_0000; else Rd \leftarrow $2^{bp}$ - 1;

Syntax: I. satrndu Rd >> sa, bp

Operands: I. d \in {0, 1, ..., 15} {sa, bp} \in {0, 1, ..., 31}

Status Flags: Q: Set if saturation occurred or Q was already set, cleared otherwise. V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode: 32000D-04/2011 ATMEL 319

SATS – Saturate Signed

Description

This instruction considers the value in (Rd>>sa)[bp-1:0] as a signed value. If the value in (Rd>>sa)[31:bp] is not merely a sign-extention of this value, overflow has occurred and saturation is performed to the maximum signed positive or negative value. If saturation occurs, the Q flag is set. An arithmetic shift is performed on Rd. If bp equals zero, no saturation is performed.

Operation:

I. Temp \leftarrow Rd >> sa If ((Temp == SE( Temp[bp-1:0])) || (bp == 0)) Rd \leftarrow Temp; else if (Temp[31] == 1) Rd \leftarrow -2$^{bp-1}$; else Rd \leftarrow 2$^{bp-1}$ - 1;

Syntax:

I. sats Rd >> sa, bp

Operands:

I. d \in {0, 1, ..., 15} {sa, bp} \in {0, 1, ..., 31}

Status Flags:

Q: Set if saturation occurred or Q was already set, cleared otherwise. V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | | Rd | | | 15 12 11 10 9 5 4 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | | bp | | | | | sa | | |

320 AVR32 32000D–04/2011

SATSUB.H – Saturated Subtract of Halfwords

Description Performs a subtraction of the specified halfwords and stores the result in destination register. The result is saturated if it overflows the range representable with 16 bits. If saturation occurs, the Q flag is set.

Operation: I. temp \leftarrow ZE(Rx[15:0]) - ZE(Ry[15:0]); if (Rx[15] \land \negRy[15] \land \negtemp[15]) \lor (\negRx[15] \land Ry[15] \land temp[15]) then if Rx[15]==0 then Rd \leftarrow 0x00007fff; else Rd \leftarrow 0xffff8000; else Rd \leftarrow SE(temp[15:0]);

Syntax: I. satsub.hRd, Rx, Ry

Operands: I. {d, s} \in {0, 1, ..., 15}

Status Flags: Q: Q \leftarrow (Rx[15] \land \negRy[15] \land \negtemp[15]) \lor (\negRx[15] \land Ry[15] \land temp[15]) \lor Q V: V \leftarrow (Rx[15] \land \negRy[15] \land \negtemp[15]) \lor (\negRx[15] \land Ry[15] \land temp[15]) N: N \leftarrow Rd[15] Z: Z \leftarrow (Rd[15:0] == 0) C: C \leftarrow 0

Opcode: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 12 11 4 3 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | Rd |

32000D–04/2011 ATMEL® 321

SATSUB.W – Saturated Subtract of Words

Description

Performs a subtraction and stores the result in destination register. The result is saturated if a two’s complement overflow occurs. If saturation occurs, the Q flag is set.

Operation:

I. temp \leftarrow Rx - Ry; II. temp \leftarrow Rs - SE(imm16));

Format I: OP1 = Rx, OP2 = Ry Format II: OP1 = Rs, OP2 = SE(imm16)

if (OP1[31] \wedge \negOP2[31] \wedge \negtemp[31]) \vee (\negOP1[31] \wedge OP2[31] \wedge temp[31]) then if(OP1[31]==0) then Rd \leftarrow 0x7fffffff; else Rd \leftarrow 0x80000000; else Rd \leftarrow temp

Syntax:

I. satsub.w Rd, Rx, Ry II. satsub.w Rd, Rs, imm

Operands:

I. {d, x, y} \in {0, 1, ..., 15} II. {d, s} \in {0, 1, ..., 15} imm \in {-32768, -32767, ..., 32767}

Status Flags:

Format I: OP1 = Rx, OP2 = Ry Format II: OP1 = Rs, OP2 = SE(imm16)

Q: Q \leftarrow (OP1[31] \wedge \negOP2[31] \wedge \negtemp[31]) \vee (\negOP1[31] \wedge OP2[31] \wedge temp[31]) \vee

V: V \leftarrow (OP1[31] \wedge \negOP2[31] \wedge \negtemp[31]) \vee (\negOP1[31] \wedge OP2[31] \wedge temp[31])

N: N \leftarrow Rd[31]

Z: Z \leftarrow (Rd[31:0] == 0)

C: C \leftarrow 0

Opcode:

322 AVR32 32000D-04/2011

AVR32

Format I: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 12 11 4 3 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | Rd |

Format II: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rs | 0 | 1 | 1 | 0 | 1 | Rd | 15 0 | imm16 |

32000D–04/2011 ATMEL® 323

SATU – Saturate Unsigned

Description

This instruction considers the value in (Rd>>sa)[bp-1:0] as a unsigned value. If the value in (Rd>>sa)[31:bp] is not merely a zero extentation of this value, overflow has occurred and saturation is performed to the maximum unsigned positive value or zero. If saturation occurs, the Q flag is set. An arithmetic shift is performed on Rd. If bp equals zero, no saturation is performed.

Operation:

I. Temp \leftarrow Rd >> sa If ((Temp == ZE( Temp[bp-1:0])) || (bp == 0) ) Rd \leftarrow Temp; else if (Temp[31] == 1) Rd \leftarrow 0x0000_0000; else Rd \leftarrow $2^{bp}$ - 1;

Syntax:

I. satu Rd >> sa, bp

Operands:

I. d \in {0, 1, ..., 15} {sa, bp} \in {0, 1, ..., 31}

Status Flags:

Q: Set if saturation occurred or Q was already set, cleared otherwise. V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \multicolumn{16}{l}{31 \hspace{4em} 29 \hspace{3em} 28 \hspace{4em} 25 \hspace{3em} 24 \hspace{4em} 20 \hspace{3em} 19 \hspace{4em} 16} \ \hline 1 & 1 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & 1 & 1 & \multicolumn{4}{c|}{Rd} \ \hline \end{tabular}

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \multicolumn{16}{l}{15 \hspace{4em} 12 \hspace{3em} 11 \hspace{3em} 10 \hspace{3em} 9 \hspace{4em} 5 \hspace{3em} 4 \hspace{4em} 0} \ \hline 0 & 0 & 0 & 0 & 0 & 1 & \multicolumn{6}{c|}{bp} & \multicolumn{4}{c|}{sa} \ \hline \end{tabular}

324 AVR32 32000D-04/2011

SBC – Subtract with Carry

Description Subtracts a specified register and the value of the carry bit from a destination register and stores the result in the destination register.

Operation: I. Rd ← Rx - Ry - C;

Syntax: I. sbc Rd, Rx, Ry

Operands: I. {x, y, d} ∈ {0, 1, ..., 15}

Status Flags: Q: Not affected. V: V ← (Rx[31] ∧ ¬Ry[31] ∧ ¬RES[31]) ∨ (¬Rx[31] ∧ Ry[31] ∧ RES[31]) N: N ← RES[31] Z: Z ← (RES[31:0] == 0) ∧ Z C: C ← ¬Rx[31] ∧ Ry[31] ∨ Ry[31] ∧ RES[31] ∨ ¬Rx[31] ∧ RES[31]

Opcode: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 12 11 4 3 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | Rd |

32000D–04/2011 ATMEL® 325

SBR – Set Bit in Register

Description Sets a bit in the specified register. All other bits are unaffected.

Operation: I. Rd[bp5] \leftarrow 1;

Syntax: I. sbr Rd, bp

Operands: I. d \in {0, 1, ..., 15} bp \in {0, 1, ..., 31}

Status Flags: Q: Not affected V: Not affected N: Not affected Z: Z \leftarrow 0 C: Not affected

Opcode: \begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & & 13 & \multicolumn{6}{c|}{12 \hspace{4em} 9} & 8 & & & 5 & 4 & 3 & 0 \ \hline 1 & 0 & 1 & \multicolumn{6}{c|}{bp[4:1]} & 1 & 1 & 0 & 1 & bp[0] & \multicolumn{3}{c|}{Rd} \ \hline \end{tabular}

326 AVR32 32000D–04/2011

AVR32

SCALL – Supervisor Call

Description

The scall instruction performs a supervisor routine call. The behaviour of the instruction is dependent on the mode it is called from, allowing scall to be executed from all contexts. Scall jumps to a dedicated entry point relative to EVBA. Scall can use the same call convention as regular subprogram calls.

Operation:

I. If ( SR[M2:M0] == {B'000 or B'001} ) If (microarchitecture == AVR32A) *(--SP${SYS}$) \leftarrow PC + 2; *(--SP${SYS}$) \leftarrow SR; PC \leftarrow EVBA + 0x100; SR[M2:M0] \leftarrow B'001; else RAR${SUP}$ \leftarrow PC + 2; RSR${SUP}$ \leftarrow SR; PC \leftarrow EVBA + 0x100; SR[M2:M0] \leftarrow B'001; else LR$_{Current Context}$ \leftarrow PC + 2; PC \leftarrow EVBA + 0x100;

Syntax:

I. scall

Operands:

I. none

Status Flags:

Q: Not affected V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode:

\begin{tabular}{|c|c|c|c|c|c|c|c||c|c|c|c|c||c|c|c|c|} \hline 1 & 1 & 0 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & 1 \ \hline \end{tabular} 15 \hspace{6em} 9 \hspace{3.5em} 8 \hspace{3.5em} 4 \hspace{3.5em} 3 \hspace{3.5em} 0

32000D-04/2011 ATMEL 327

SCR – Subtract Carry from Register

Description Subtracts carry from the specified destination register.

Operation: I. Rd \leftarrow Rd - C;

Syntax: I. scr Rd

Operands: I. d \in {0, 1, ..., 15}

Status Flags: Q: Not affected V: V \leftarrow (Rd[31] \wedge \negRES[31]) N: N \leftarrow RES[31] Z: Z \leftarrow (RES[31:0] == 0) \wedge Z C: C \leftarrow \negRd[31] \wedge RES[31]

Opcode: 15 13 12 4 3 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | | | Rd | | |

Example ; Subtract a 32-bit variable (R0) from a 64-bit variable (R2:R1) sub R1, R0 scr R2

328 AVR32 32000D–04/2011

SLEEP – Set CPU Activity Mode

Description Sets the system in the sleep mode specified by the implementation defined Op8 operand. The semantic of Op8 is IMPLEMENTATION DEFINED. If bit 7 in Op8 is one, SR[GM] will be cleared when entering sleep mode.

Operation: I. Set the system in the specified sleep mode.

Syntax: I. sleep Op8

Operands: I. Op8 ∈ {0, 1, ..., 255}

Status Flags: Q: Not affected V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode: Note: The sleep instruction is a privileged instruction, and will trigger a Privilege Violation exception if executed in user mode.

32000D–04/2011 ATMEL® 329

SR{cond4} – Set Register Conditionally

Description Sets the register specified to 1 if the condition specified is true, clear the register otherwise.

Operation: I. if (cond4) Rd \leftarrow 1; else Rd \leftarrow 0;

Syntax: I. sr{cond4} Rd

Operands: I. cond4 \in {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} d \in {0, 1, ..., 15}

Status Flags: Q: Not affected V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode: 330 AVR32 32000D-04/2011

AVR32

SSCALL – Secure State Call

Architecture revision 3 and higher.

Description The sscall instruction performs a secure state call. Sscall can use the same call convention as regular subprogram calls.

Operation: I. SS_RAR \leftarrow PC; SS_RSR \leftarrow SR; If (microarchitecture == AVR32A) PC \leftarrow 0x8000_0004; else) PC \leftarrow 0xA000_0004; SR[SS] \leftarrow 1; SR[GM] \leftarrow 1; if (SR[M2:M0] == 0) SR[M2:M0] \leftarrow 001;

Syntax: I. sscall

Operands: I. none

Status Flags: Q: Not affected V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode: \begin{tabular}{|c|c|c|c|c|c|c|c||c|c|c|c|c|c|c|c|} \multicolumn{8}{c}{15 \quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad\quad 9} & \multicolumn{1}{c}{8} & \multicolumn{5}{c}{4 \quad\quad\quad 3} & \multicolumn{2}{c}{0} \ \hline 1 & 1 & 0 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 1 & 1 \ \hline \end{tabular}

32000D-04/2011 ATMEL 331

SSRF – Set Status Register Flag

Description Sets the status register (SR) flag specified.

Operation: I. SR[bp5] \leftarrow 1;

Syntax: I. ssrf bp

Operands: I. bp \in {0, 1, ..., 31}

Status Flags: SR[bp5] \leftarrow 1, all other flags unchanged.

Opcode: \begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & & & & 11 & 10 & 9 & 8 & & & & & 4 & 3 & & 0 \ \hline 1 & 1 & 0 & 1 & 0 & 0 & 1 & & & & & & bp5 & & 0 & 0 & 1 & 1 \ \hline \end{tabular}

Note: Privileged if bp5 > 15, ie. upper half of status register. An exception will be triggered if the upper half of the status register is attempted changed in user mode.

332 AVR32 32000D–04/2011

ST.B – Store Byte

Description The source register is stored to the byte memory location referred to by the pointer address.

Operation: I. *(Rp) \leftarrow Rs[7:0]; Rp \leftarrow Rp + 1; II. Rp \leftarrow Rp - 1; *(Rp) \leftarrow Rs[7:0]; III. *(Rp + ZE(disps)) \leftarrow Rs[7:0]; IV. *(Rp + SE(disp16)) \leftarrow Rs[7:0]; V. *(Rb + (Ri << sa2)) \leftarrow Rs[7:0];

Syntax: I. st.b Rp++, Rs II. st.b --Rp, Rs III. st.b Rp[disp], Rs IV. st.b Rp[disp], Rs V. st.b Rb[Ri << sa], Rs

Operands: I, II. {s , p} \in {0, 1, ..., 15} III. {s , p} \in {0, 1, ..., 15} disp \in {0, 1, ..., 7} IV. {s , p} \in {0, 1, ..., 15} disp \in {-32768, -32767, ..., 32767} V. {b, i, s} \in {0, 1, ..., 15} sa \in {0, 1, 2, 3}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: 15 13 12 9 8 4 3 0 | 0 | 0 | 0 | Rp | 0 | 1 | 1 | 0 | 0 | Rs |

32000D-04/2011 ATMEL 333

ATMEL

Format II: 15 13 12 9 8 4 3 0 | 0 | 0 | 0 | Rp | 0 | 1 | 1 | 1 | 1 | Rs |

Format III: 15 13 12 9 8 7 6 4 3 0 | 1 | 0 | 1 | Rp | 0 | 1 | disp3 | Rs |

Format IV: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rp | 1 | 0 | 1 | 1 | 0 | Rs | 15 0 | disp16 |

Format V: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rb | 0 | 0 | 0 | 0 | 0 | Ri | 15 12 11 8 7 6 5 4 3 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | Shift Amount | Rs |

Note: For formats I. and II., if Rp = Rs the result will be UNDEFINED.

334 AVR32 32000D–04/2011

ST.B{cond4} – Conditionally Store Byte

Architecture revision 2 and higher.

Description The source register is stored to the byte memory location referred to by the pointer address if the given condition is satisfied.

Operation: I. if (cond4) *(Rp + ZE(disp9)) \leftarrow Rs[7:0];

Syntax: I. st.b{cond4} Rp[disp], Rs

Operands: I. s, p \in {0, 1, ..., 15} disp \in {0, 1, ..., 511} cond4 \in {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rp | 1 | 1 | 1 | 1 | 1 | Rd | 15 12 11 8 7 6 5 4 3 0 | cond4 | 1 | 1 | 1 | disp9 |

32000D–04/2011 335

ST.D – Store Doubleword

Description

The source registers are stored to the doubleword memory location referred to by the pointer address.

Operation:

I. *(Rp) \leftarrow Rs+1:Rs; Rp \leftarrow Rp + 8; II. Rp \leftarrow Rp - 8; *(Rp) \leftarrow Rs+1:Rs; III. *(Rp) \leftarrow Rs+1:Rs; IV. *(Rp + SE(displ6)) \leftarrow Rs+1:Rs; V. *(Rb + (Ri << sa2)) \leftarrow Rs+1:Rs;

Syntax:

I. st.d Rp++, Rs II. st.d --Rp, Rs III. st.d Rp, Rs IV. st.d Rp[disp], Rs V. st.d Rb[Ri << sa], Rs

Operands:

I, II, III. p \in {0, 1, ..., 15} s \in {0, 2, ..., 14} IV. p \in {0, 1, ..., 15} s \in {0, 2, ..., 14} disp \in {-32768, -32767, ..., 32767} V. {b, i} \in {0, 1, ..., 15} s \in {0, 2, ..., 14} sa \in {0, 1, 2, 3}

Status Flags:

Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

336 AVR32 32000D-04/2011

AVR32

Format I: 15 13 12 9 8 6 5 4 3 1 0 | 1 | 0 | 1 | Rp | 1 | 0 | 0 | 1 | 0 | Rs | 0 |

Format II: 15 13 12 9 8 6 5 4 3 1 0 | 1 | 0 | 1 | Rp | 1 | 0 | 0 | 1 | 0 | Rs | 1 |

Format III: 15 13 12 9 8 4 3 0 | 1 | 0 | 1 | Rp | 1 | 0 | 0 | 0 | 1 | Rs | 1 |

Format IV: 31 29 28 25 24 20 19 17 16 | 1 | 1 | 1 | Rp | 0 | 1 | 1 | 1 | 0 | Rs | 1 | 15 0 | disp16 |

Format V: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rb | 0 | 0 | 0 | 0 | 0 | Ri | 15 12 11 8 7 6 5 4 3 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Shift Amount | Rs |

Note: For formats I. and II., if Rp == Rs the result will be UNDEFINED.

32000D–04/2011 337

ST.H – Store Halfword

Description The source register is stored to the halfword memory location referred to by the pointer address.

Operation: I. *(Rp) \leftarrow Rs[15:0]; Rp \leftarrow Rp + 2; II. Rp \leftarrow Rp - 2; *(Rp) \leftarrow Rs[15:0]; III. *(Rp + ZE(disp3 \ll 1)) \leftarrow Rs[15:0]; IV. *(Rp + SE(disp16)) \leftarrow Rs[15:0]; V. *(Rb + (Ri \ll sa2)) \leftarrow Rs[15:0];

Syntax: I. st.h Rp++, Rs II. st.h --Rp, Rs III. st.h Rp[disp], Rs IV. st.h Rp[disp], Rs V. st.h Rb[Ri \ll sa], Rs

Operands: I, II. {s , p} \in {0, 1, ..., 15} III. {s , p} \in {0, 1, ..., 15} disp \in {0, 2, ..., 14} IV. {s , p} \in {0, 1, ..., 15} disp \in {-32768, -32767, ..., 32767} V. {b, i, s} \in {0, 1, ..., 15} sa \in {0, 1, 2, 3}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: 338 AVR32 32000D-04/2011

Format II: 15 13 12 9 8 4 3 0 | 0 | 0 | 0 | Rp | 0 | 1 | 1 | 1 | 0 | Rs |

Format III: 15 13 12 9 8 7 6 4 3 0 | 1 | 0 | 1 | Rp | 0 | 0 | disp3 | Rs |

Format IV: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rp | 1 | 0 | 1 | 0 | 1 | Rs | 15 0 | disp16 |

Format V: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rb | 0 | 0 | 0 | 0 | 0 | Ri | 15 12 11 8 7 6 5 4 3 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | Shift Amount | Rs |

Note: For formats I. and II., if Rp == Rs the result will be UNDEFINED.

32000D–04/2011 339

ST.H{cond4} – Conditionally Store Halfword

Architecture revision 2 and higher.

Description

The source register is stored to the halfword memory location referred to by the pointer address if the given condition is satisfied.

Operation:

1. if (cond4) *(Rp + ZE(disp9<<1)) ← Rs[15:0];

Syntax:

1. st.h{cond4} Rp[disp], Rs

Operands:

1. s, p ∈ {0, 1, ..., 15} disp ∈ {0, 2, ..., 1022} cond4 ∈ {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}

Status Flags:

Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rp | 1 | 1 | 1 | 1 | 1 | Rs | 15 12 11 8 7 6 5 4 3 0 | cond4 | 1 | 1 | 0 | disp9 |

340 AVR32 32000D–04/2011

ST.W – Store Word

Description

The source register is stored to the word memory location referred to by the pointer address.

Operation:

I.
  *(Rp) ← Rs;
  Rp ← Rp + 4;
II.
  Rp ← Rp - 4;
  *(Rp) ← Rs;
III.
  *(Rp + ZE(disp4 << 2)) ← Rs;
IV.
  *(Rp + SE(disp16)) ← Rs;
V.
  *(Rb + (Ri << sa2)) ← Rs;

Syntax:

I.
  st.w  Rp++, Rs
II.
  st.w  --Rp, Rs
III.
  st.w  Rp[disp], Rs
IV.
  st.w  Rp[disp], Rs
V.
  st.w  Rb[Ri << sa], Rs

Operands:

I, II.
  {s , p} ∈ {0, 1, ..., 15}
III.
  {s , p} ∈ {0, 1, ..., 15}
  disp ∈ {0, 4, ..., 60}
IV.
  {s , p} ∈ {0, 1, ..., 15}
  disp ∈ {-32768, -32767,..., 32767}
V.
  {b, i, s} ∈ {0, 1, ..., 15}
  sa ∈ {0, 1, 2, 3}

Status Flags:

Q:  Not affected.
V:  Not affected.
N:  Not affected.
Z:  Not affected.
C:  Not affected.

Opcode:

Format I:

Format II:

Format III:

Format IV:

Format V:

Note: For formats I. and II., if Rp == Rs the result will be UNDEFINED.

ST.W{cond4} – Conditionally Store Word

Architecture revision 2 and higher.

Description The source register is stored to the word memory location referred to by the pointer address if the given condition is satisfied.

Operation: I. if (cond4) *(Rp + ZE(disp9<<2)) \leftarrow Rs;

Syntax: I. st.w{cond4} Rp[disp], Rs

Operands: I. s, p \in {0, 1, ..., 15} disp \in {0, 4, ..., 2044} cond4 \in {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rp | 1 | 1 | 1 | 1 | 1 | Rd | 15 12 11 8 7 6 5 4 3 0 | cond4 | 1 | 0 | 1 | disp9 |

32000D–04/2011 343