Atmel AVR32 user guide: BREV – Bit Reverse

BREV – Bit Reverse

Description Bit-reverse the contents in the register.

Operation: I. Rd[31:0] \leftarrow Rd[0:31];

Syntax: I. brev Rd

Operands: I. d \in {0, 1, ..., 15}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Z \leftarrow (RES[31:0] == 0) C: Not affected.

Opcode:

146 AVR32 32000D–04/2011

BST – Copy C to register bit

Description Copy the C-flag to an arbitrary bit in a register.

Operation: I. Rd[bp5] \leftarrow C;

Syntax: I. bst Rd, bp

Operands: I. d \in {0, 1, ..., 15} bp \in {0, 1, ..., 31}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | | | Rd | | | 15 5 4 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Bit Position | | |

32000D–04/2011 ATMEL® 147

CACHE – Perform Cache control operation

Description Control cache operation.

Operation: I. Issue a command to the cache

Syntax: I. cache Rp[disp], Op5

Operands: I. disp ∈ {-1024, -1023, ..., 1023} p ∈ {0, 1, ..., 15}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Note: This instruction can only be executed in a privileged mode. Execution from any other mode will trigger a Privilege Violation exception.

32000D-04/2011 ATMEL 149

CASTS.{H,B} – Typecast to Signed Word

Description

Sign extends the halfword or byte that is specified to word size. The result is stored back to the specified register.

Operation:

I. Rd[31:16] \leftarrow Rd[15]; II. Rd[31:8] \leftarrow Rd[7];

Syntax:

I. casts.h Rd II. casts.b Rd

Operands:

I, II. d \in {0, 1, ..., 15}

Status Flags:

Q: Not affected. V: Not affected. N: N \leftarrow RES[31] Z: Z \leftarrow (RES[31:0] == 0) C: C \leftarrow RES[31]

Opcode:

Format I:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & & 13 & 12 & & & & 9 & 8 & & & & & 4 & 3 & 0 \ \hline 0 & 1 & 0 & 1 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & & & Rd & \ \hline \end{tabular}

Format II:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & & 13 & 12 & & & & 9 & 8 & & & & & 4 & 3 & 0 \ \hline 0 & 1 & 0 & 1 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & & & Rd & \ \hline \end{tabular}

AVR32

CASTU.{H,B} – Typecast to Unsigned Word

Description Zero extends the halfword or byte that is specified to word size. The result is stored back to the specified register.

Operation: I. Rd[31:16] \leftarrow 0; II. Rd[31:8] \leftarrow 0:

Syntax: I. castu.h Rd II. castu.b Rd

Operands: I, II. d \in {0, 1, ..., 15}

Status Flags: Q: Not affected. V: Not affected. N: N \leftarrow RES[31] Z: Z \leftarrow (RES[31:0] == 0) C: C \leftarrow RES[31]

Opcode: Format I: Format II:

32000D-04/2011 ATMEL 151

CBR – Clear Bit in Register

Description Clears a bit in the specified register. All other bits are unaffected.

Operation: I. Rd[bp5] \leftarrow 0;

Syntax: I. cbr Rd, bp

Operands: I. d \in {0, 1, ..., 15} bp \in {0, 1, ..., 31}

Status Flags: Q: Not affected V: Not affected N: Not affected Z: Z \leftarrow (RES[31:0] == 0) C: Not affected

Opcode: \begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & \multicolumn{2}{c|}{13} & 12 & \multicolumn{4}{c|}{9} & 8 & \multicolumn{2}{c|}{5} & 4 & \multicolumn{2}{c|}{3} & \multicolumn{3}{c|}{0} \ \hline 1 & 0 & 1 & \multicolumn{4}{c|}{Bit[4:1]} & 1 & 1 & 1 & 0 & Bit[0] & \multicolumn{4}{c|}{Rd} \ \hline \end{tabular}

152 AVR32 32000D–04/2011

AVR32

CLZ – Count Leading Zeros

Description Counts the number of binary zero bits before the first binary one bit in a register value. The value returned from the operation can be used for doing normalize operations. If the operand is zero, the value 32 is returned.

Operation: I. temp \leftarrow 32; for (i = 31; i >= 0; i--) if (Rs[i] == 1) then temp \leftarrow 31 - i; break; Rd \leftarrow temp;

Syntax: I. clz Rd, Rs

Operands: I. {d, s} \in {0, 1, ..., 15}

Status Flags Q: Not affected V: Not affected N: Not affected Z: Z \leftarrow (RES[31:0] == 0) C: C \leftarrow (RES[31:0] == 32)

Opcode:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rs | 0 | 0 | 0 | 0 | 0 | Rd | 15 12 11 8 7 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |

32000D-04/2011 ATMEL® 153

ATMEl

COM – One’s Compliment

Description Perform a one’s complement of specified register.

Operation: I. Rd ← ¬Rd;

Syntax: I. com Rd

Operands: I. d ∈ {0, 1, ..., 15}

Status Flags: Q: Not affected V: Not affected N: Not affected Z: Z ← (RES[31:0] == 0) C: Not affected

Opcode:

15 13 12 9 8 4 3 0 0 1 0 | 1 1 1 0 | 0 1 1 0 1 | Rd

154 AVR32 32000D–04/2011

COP – Coprocessor Operation

Description Addresses a coprocessor and performs the specified operation on the specified registers.

Operation: I. CP#(CRd) \leftarrow CP#(CRx) Op CP#(CRy);

Syntax: I. cop CP#, CRd, CRx, CRy, Op

Operands: I. # \in {0, 1, ..., 7} Op \in {0, 1, ..., 127} {d, x, y} \in {0, 1, ..., 15}

Status Flags: Q: Coprocessor-specific V: Coprocessor-specific N: Coprocessor-specific Z: Coprocessor-specific C: Coprocessor-specific

Opcode: Example: cop CP2, CR0, CR1, CR2, 0

32000D–04/2011 ATMEL® 155

CP.B – Compare Byte

Description

Performs a compare between the lowermost bytes in the two operands specified. The operation is implemented by doing a subtraction without writeback of the difference. The operation sets the status flags according to the result of the subtraction, but does not affect the operand registers.

Operation: I. Rd[7:0] - Rs[7:0];

Syntax: I. cp.b Rd, Rs

Operands: I. {d, s} ∈ {0, 1, ..., 15}

Status Flags: Q: Not affected V: V \leftarrow (Rd[7] \land \neg Rs[7] \land \neg RES[7]) \lor (\neg Rd[7] \land Rs[7] \land RES[7]) N: N \leftarrow RES[7] Z: Z \leftarrow (RES[7:0] == 0) C: C \leftarrow \neg Rd[7] \land Rs[7] \lor Rs[7] \land RES[7] \lor \neg Rd[7] \land RES[7]

Opcode

CP.H – Compare Halfword

Description Performs a compare between the lowermost halfwords in the two operands specified. The operation is implemented by doing a subtraction without writeback of the difference. The operation sets the status flags according to the result of the subtraction, but does not affect the operand registers.

Operation: I. Rd[15:0] - Rs[15:0];

Syntax: I. cp.h Rd, Rs

Operands: I. {d, s} ∈ {0, 1, ..., 15}

Status Flags: Format I: OP1 = Rd, OP2 = Rs Q: Not affected V: V \leftarrow (OP1[15] \wedge ¬OP2[15] \wedge ¬RES[15]) \vee (¬OP1[15] \wedge OP2[15] \wedge RES[15]) N: N \leftarrow RES[15] Z: Z \leftarrow (RES[15:0] == 0) C: C \leftarrow ¬OP1[15] \wedge OP2[15] \vee OP2[15] \wedge RES[15] \vee ¬OP1[15] \wedge RES[15]

Opcode

32000D-04/2011 ATMEL 157

CP.W – Compare Word

Description

Performs a compare between the two operands specified. The operation is implemented by doing a subtraction without writeback of the difference. The operation sets the status flags according to the result of the subtraction, but does not affect the operand registers.

Operation: I. Rd - Rs; II. Rd - SE(imm6); III. Rd - SE(imm21);

Syntax: I. cp.w Rd, Rs II. cp.w Rd, imm III. cp.w Rd, imm

Operands: I. {d, s} ∈ {0, 1, ..., 15} II. d ∈ {0, 1, ..., 15} imm ∈ {-32, -31, ..., 31} III. d ∈ {0, 1, ..., 15} imm ∈ {-1048576, -104875, ..., 1048575}

Status Flags: Format I: OP1 = Rd, OP2 = Rs Format II: OP1 = Rd, OP2 = SE(imm6) Format III: OP1 = Rd, OP2 = SE(imm21) Q: Not affected V: V \leftarrow (OP1[31] \land \lnot OP2[31] \land \lnot RES[31]) \lor (\lnot OP1[31] \land OP2[31] \land RES[31]) N: N \leftarrow RES[31] Z: Z \leftarrow (RES[31:0] == 0) C: C \leftarrow \lnot OP1[31] \land OP2[31] \lor OP2[31] \land RES[31] \lor \lnot OP1[31] \land RES[31]

Opcode

Format I:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & & 13 & 12 & & & & 9 & 8 & & & & 4 & 3 & & 0 \ \hline 0 & 0 & 0 & \multicolumn{4}{c|}{Rs} & 0 & 0 & 0 & 1 & 1 & \multicolumn{2}{c|}{Rd} \ \hline \end{tabular}

Format II:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & & 13 & 12 & & 10 & 9 & & & & & & 4 & 3 & & 0 \ \hline 0 & 1 & 0 & 1 & 1 & 0 & \multicolumn{6}{c|}{imm6} & & & \multicolumn{2}{c|}{Rd} \ \hline \end{tabular}

Format III: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | imm21[20:17 | 0 | 0 | 1 | 0 | i21[16] | | Rd | | | | | 15 0 | | | | | | | | | imm21[15:0 | | | | | | | |

32000D–04/2011 ATMEL® 159

ATME

CPC – Compare with Carry

Description

Performs a compare between the two registers specified. The operation is executed by doing a subtraction with carry (as borrow) without writeback of the difference. The operation sets the status flags according to the result of the subtraction, but does not affect the operand registers. Note that the zero flag status before the operation is included in the calculation of the new zero flag. This instruction allows large compares (64, 128 or more bits).

Operation:

I. Rd - Rs - C; II. Rd - C;

Syntax:

I. cpc Rd, Rs II. cpc Rd

Operands:

I. {d, s} ∈ {0, 1, ..., 15} II. d ∈ {0, 1, ..., 15}

Status Flags:

In format II, Rs referred to below equals zero. Q: Not affected V: V \leftarrow (Rd[31] \land \neg Rs[31] \land \neg RES[31]) \lor (\neg Rd[31] \land Rs[31] \land RES[31]) N: N \leftarrow RES[31] Z: Z \leftarrow (RES[31:0] == 0) \land Z C: C \leftarrow \neg Rd[31] \land Rs[31] \lor Rs[31] \land RES[31] \lor \neg Rd[31] \land RES[31]

Opcode:

Format I: Format II:

160 AVR32 32000D-04/2011

CSRF – Clear Status Register Flag

Description Clears the status register (SR) flag specified.

Operation: I. SR[bp5] \leftarrow 0;

Syntax: I. csrf bp

Operands: I. bp \in {0, 1, ..., 31}

Status Flags: SR[bp5] \leftarrow 0, all other flags unchanged.

Opcode:

Note: Privileged if bp5 > 15, ie. upper half of status register. An exception will be triggered if the upper half of the status register is attempted changed in user mode.

32000D–04/2011 ATMEL ® 161

CSRFCZ – Copy Status Register Flag to C and Z

Description Copies the status register (SR) flag specified to C and Z.

Operation: I. C \leftarrow SR[bp5]; Z \leftarrow SR[bp5];

Syntax: I. csrfcz bp

Operands: I. bp \in {0, 1, ..., 31}

Status Flags: Q: Not affected V: Not affected N: Not affected Z: Z \leftarrow SR[bp5] C: C \leftarrow SR[bp5]

Opcode: Note: Privileged if bp5 > 15, ie. upper half of status register. A Privilege Violation exception will be triggered if the upper half of the status register is attempted read in user mode.

162 AVR32 32000D–04/2011

DIVS – Signed divide

Description Performs a signed divide between the two 32-bit register specified. The quotient is returned in Rd, the remainder in Rd+1. No exceptions are taken if dividing by 0. Result in Rd and Rd+1 is UNDEFINED when dividing by 0. The sign of the remainder will be the same as the dividend, and the quotient will be negative if the signs of Rx and Ry are opposite.

Operation: I. Rd \leftarrow Rx / Ry; Rd+1 \leftarrow Rx % Ry;

Syntax: I. divs Rd, Rx, Ry

Operands: I. d \in {0, 2, ..., 14} {x, y} \in {0, 1, ..., 15}

Status Flags Q: Not affected V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 12 11 4 3 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Rd |

32000D–04/2011 ATMEL® 163

ATMEL

DIVU – Unsigned divide

Description Performs an unsigned divide between the two 32-bit register specified. The quotient is returned in Rd, the remainder in Rd+1. No exceptions are taken if dividing by 0. Result in Rd and Rd+1 is UNDEFINED when dividing by 0.

Operation: I. Rd \leftarrow Rx / Ry; Rd+1 \leftarrow Rx % Ry;

Syntax: I. divu Rd, Rx, Ry

Operands: I. d \in {0, 2, ..., 14} {x, y} \in {0, 1, ..., 15}

Status Flags Q: Not affected V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode: \begin{tabular}{|c c c c c c c c c c c c c c c c|} \hline 31 & & 29 & 28 & & & & 25 & 24 & & & & & 20 & 19 & & 16 \ \hline 1 & 1 & 1 & & R x & & & & 0 & 0 & 0 & 0 & 0 & & R y & & \ \hline \end{tabular}

\begin{tabular}{|c c c c c c c c c c c c c c c c|} \hline 15 & & 12 & 11 & & & & 4 & 3 & & & & & 0 \ \hline 0 & 0 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & & R d & & \ \hline \end{tabular}

164 AVR32 32000D–04/2011

AVR32

EOR – Logical Exclusive OR with optional logical shift

Description Performs a bitwise logical Exclusive-OR between the specified registers and stores the result in the destination register.

Operation: I. Rd \leftarrow Rd \oplus Rs; II. Rd \leftarrow Rx \oplus (Ry << sa5); III. Rd \leftarrow Rx \oplus (Ry >> sa5);

Syntax: I. eor Rd, Rs II. eor Rd, Rx, Ry << sa III. eor Rd, Rx, Ry >> sa

Operands: I. {d, s} \in {0, 1, ..., 15} II, III. {d, x, y} \in {0, 1, ..., 15} sa \in {0, 1, ..., 31}

Status Flags Q: Not affected V: Not affected N: N \leftarrow RES[31] Z: Z \leftarrow (RES[31:0] == 0) C: Not affected

Opcode: Format I: Format II:

32000D-04/2011 ATMEL 165

ATMEL

Format III: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 1 | 1 | 1 | 1 | 0 | Ry | 15 9 8 4 3 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | sa5 | Rd |

166 AVR32 32000D–04/2011

AVR32

EOR{cond4} – Conditional Logical EOR

Architecture revision 2 and higher.

Description Performs a bitwise logical Exclusive-OR between the specified registers and stores the result in the destination register.

Operation:

1. if ( cond4) Rd \leftarrow Rx \oplus Ry;

Syntax:

1. eor{cond4} Rd, Rx, Ry

Operands:

1. {d, x, y} \in {0, 1, ..., 15} cond4 \in {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |......| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |......| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |......

EORH, EORL – Logical EOR into high or low half of register

Description Performs a bitwise logical Exclusive-OR between the high or low halfword in the specified register and a constant. The result is stored in the destination register.

Operation: I. Rd[31:16] \leftarrow Rd[31:16] \oplus imm16 II. Rd[15:0] \leftarrow Rd[15:0] \oplus imm16

Syntax: I. eorh Rd, imm II. eorl Rd, imm

Operands: I, II. d \in {0, 1, ..., 15} imm \in {0, 1, ..., 65535}

Status Flags: Q: Not affected V: Not affected N: N \leftarrow RES[31] Z: Z \leftarrow (RES[31:0] == 0) C: Not affected

Opcode Format I: Format II:

168 AVR32 32000D–04/2011

FRS – Flush Return Stack

Description Special instruction to invalidate the return address stack. This instruction is used when the user writes code that conflicts with the semantics required by the return address stack.

Operation: I. Invalidate all entries in the return address stack.

Syntax: I. frs

Operands: I. none

Status Flags: Q: Not affected V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode:

\begin{tabular}{|c|c|c|c|c|c|c|c||c|c|c|c|c|c|c|c|} \hline 1 & 1 & 0 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 1 \ \hline \end{tabular}

• 15 \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \ ........ \quad 9 \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \ ........ \quad 8 \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \ ........ \quad 4 \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \ ........ \quad 3 \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \ ........ \quad 0

Note: On implementation without a return stack this instruction will execute as a "NOP".

32000D–04/2011 \hfill 169

ATMEL

ICALL – Indirect Call to Subroutine

Description Call to a subroutine pointed to by the pointer residing in Rp.

Operation: I. LR \leftarrow PC + 2; PC \leftarrow Rd;

Syntax: I. icall Rd

Operands: I. d \in {0, 1, ..., 15}

Status Flags: Q: Not affected V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode: \begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & & 13 & 12 & & & & 9 & 8 & & & & & 4 & 3 & 0 \ \hline 0 & 1 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 1 & & & Rd & \ \hline \end{tabular}

170 AVR32 32000D–04/2011