Atmel AVR32 user guide: LDDSP – Load SP-relative with Displacement

LDDSP – Load SP-relative with Displacement

Description Reads the value of a memory location referred to by the stack pointer register and a displacement.

Operation: I. Rd \leftarrow * ( (SP && 0xFFFF_FFFC) + (ZE(disp7) << 2));

Syntax: I. Iddsp Rd, SP[disp]

Operands: I. d \in {0, 1, ..., 15} disp \in {0, 4, ..., 508}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & & 13 & 12 & 11 & \multicolumn{6}{c|}{10} & & & 4 & 3 & 0 \ \hline 0 & 1 & 0 & 0 & 0 & \multicolumn{6}{c|}{disp7} & & & & Rd & & \ \hline \end{tabular}

196 AVR32 32000D–04/2011

LDINS.{B,H} – Load and Insert Byte or Halfword into register

Description This instruction loads a byte or a halfword from memory and inserts it into the addressed byte or halfword position in Rd. The other parts of Rd are unaffected.

Operation: I. If (part == b) Rd[7:0] \leftarrow *(Rp+SE(disp12)); else if (part == l) Rd[15:8] \leftarrow *(Rp+SE(disp12)); else if (part == u) Rd[23:16] \leftarrow *(Rp+SE(disp12)); else Rd[31:24] \leftarrow *(Rp+SE(disp12)); II. If (part == b) Rd[15:0] \leftarrow *(Rp+SE(disp12) << 1); else Rd[31:16] \leftarrow *(Rp+SE(disp12) << 1);

Syntax: I. ldins.b Rd:, Rp[disp] II. ldins.h Rd:, Rp[disp]

Operands: I. {p, d} \in {0, 1, ..., 15} part \in {t, u, l, b} disp \in {-2048, -2047, ..., 2047} II. {p, d} \in {0, 1, ..., 15} part \in {t, b} disp \in {-4096, -4094, ..., 4094}

Status Flags: Q: Not affected V: Not affected N: Not affected Z: Not affected C: Not affected

32000D-04/2011 ATMEL 197

Opcode:

Format I:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rp | 1 | 1 | 1 | 0 | 1 | Rd | 15 14 13 12 11 0 | 0 | 1 | part | disp12 |

Format II:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rp | 1 | 1 | 1 | 0 | 1 | Rd | 15 13 12 11 0 | 0 | 0 | 0 | part | disp12 |

198 AVR32 32000D–04/2011

LDM – Load Multiple Registers

Description

Loads the consecutive words pointed to by Rp into the registers specified in the instruction. The PC can be loaded, resulting in a jump to the loaded target address. If PC is loaded, the return value in R12 is tested and the flags are updated. The return value may optionally be set to -1, 0 or 1.

Operation:

I. Loadaddress \leftarrow Rp; if Reglist16[PC] == 1 then if Rp == PC then Loadaddress \leftarrow SP; PC \leftarrow *(Loadaddress++); if Rp == PC then if Reglist16[LR,R12] == B'00 R12 \leftarrow 0; else if Reglist16[LR,R12] == B'01 R12 \leftarrow 1; else R12 \leftarrow -1; Test R12 and update flags; else if Reglist16[LR] == 1 LR \leftarrow *(Loadaddress++); if Reglist16[SP] == 1 SP \leftarrow *(Loadaddress++); if Reglist16[R12] == 1 R12 \leftarrow *(Loadaddress++); Test R12 and update flags; else if Reglist16[LR] == 1 LR \leftarrow *(Loadaddress++); if Reglist16[SP] == 1 SP \leftarrow *(Loadaddress++); if Reglist16[R12] == 1 R12 \leftarrow *(Loadaddress++); for (i = 11 to 0) if Reglist16[i] == 1 then Ri \leftarrow *(Loadaddress++); if Opcode[++] == 1 then if Rp == PC then SP \leftarrow Loadaddress; else Rp \leftarrow Loadaddress;

32000D-04/2011 ATMEL 199

Syntax: I. ldm Rp{++}, Reglist16

Operands: I. Reglist16 \in {R0, R1, R2, ..., R12, LR, SP, PC} p \in {0, 1, ..., 15}

Status Flags: Flags are only updated if Reglist16[PC] == 1. They are set as the result of the operation cp R12, 0.

Q: Not affected V: V \leftarrow 0 N: N \leftarrow RES[31] Z: Z \leftarrow (RES[31:0] == 0) C: C \leftarrow 0

Opcode: 31 29 28 26 25 24 20 19 16 | 1 | 1 | 1 | 0 | 0 | 0 | ++ | 1 | 1 | 1 | 0 | 0 | Rp | 15 0 |R15| R14| R13| R12| R11| R10| R9 | R8 | R7 | R6 | R5 | R4 | R3 | R2 | R1 | R0 |

Note: Emtpy Reglist16 gives UNDEFINED result. If Rp is in Reglist16 and pointer is written back the result is UNDEFINED. The R bit in the status register has no effect on this instruction.

200 AVR32 32000D-04/2011

AVR32

LDMTS – Load Multiple Registers for Task Switch

Description Loads the consecutive words pointed to by Rp into the registers specified in the instruction. The target registers reside in the User Register Context, regardless of which context the instruction is called from.

Operation: I. Loadaddress \leftarrowRp; for (i = 15 to 0) if Reglist16[i] == 1 then Ri USER \leftarrow*(Loadaddress++); if Opcode[++] == 1 then Rp \leftarrow Loadaddress;

Syntax: I. ldmts Rp{++}, Reglist16

Operands: I. Reglist16 \in {R0, R1, R2, ..., R12, LR, SP} p \in {0, 1, ..., 15}

Status Flags: Not affected.

Opcode: Note: This instruction is intended for performing task switches. Emtpy Reglist16 gives UNDEFINED result. PC in Reglist16 gives UNDEFINED result.

32000D-04/2011 ATMEL 201

LDSWP.{SH, UH, W} – Load and Swap

Description

This instruction loads a halfword or a word from memory. If a halfword load is performed, the loaded value is zero- or sign-extended. The bytes in the loaded value are shuffled and the result is written back to Rd. The instruction can be used for performing loads from memories of different endianness.

Operation:

I. temp[15:0] \leftarrow *(Rp+SE(disp12) << 1); Rd \leftarrow SE(temp[7:0], temp[15:8]); II. temp[15:0] \leftarrow *(Rp+SE(disp12) << 1); Rd \leftarrow ZE(temp[7:0], temp[15:8]); III. temp \leftarrow *(Rp+SE(disp12) << 2); Rd \leftarrow (temp[7:0], temp[15:8], temp[23:16], temp[31:24]);

Syntax:

I. ldswp.shRd, Rp[disp] II. ldswp.uhRd, Rp[disp] III. ldswp.wRd, Rp[disp]

Operands:

I, II. {d, p} \in {0, 1, ..., 15} disp \in {-4096, -4094, ..., 4094} III. {d, p} \in {0, 1, ..., 15} disp \in {-8192, -8188, ..., 8188}

Status Flags:

Q: Not affected V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode:

Format I:

202 AVR32 32000D–04/2011

Format II:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 31 & \multicolumn{2}{c|}{29} & 28 & \multicolumn{4}{c|}{Rp} & \multicolumn{2}{c|}{25} & 24 & \multicolumn{5}{c|}{} & \multicolumn{2}{c|}{20} & 19 & \multicolumn{4}{c|}{Rd} & \multicolumn{6}{c|}{16} \ \hline 1 & 1 & 1 & \multicolumn{4}{c|}{} & \multicolumn{4}{c|}{} & 1 & 1 & 1 & 0 & 1 & \multicolumn{2}{c|}{} & \multicolumn{4}{c|}{} & \multicolumn{6}{c|}{} \ \hline \multicolumn{2}{|c|}{15} & \multicolumn{2}{c|}{12} & \multicolumn{2}{c|}{11} & \multicolumn{10}{c|}{disp12} & \multicolumn{12}{c|}{0} \ \hline 0 & 0 & 1 & 1 & \multicolumn{2}{c|}{} & \multicolumn{10}{c|}{} & \multicolumn{12}{c|}{} \ \hline \end{tabular}

Format III:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 31 & \multicolumn{2}{c|}{29} & 28 & \multicolumn{4}{c|}{Rp} & \multicolumn{2}{c|}{25} & 24 & \multicolumn{5}{c|}{} & \multicolumn{2}{c|}{20} & 19 & \multicolumn{4}{c|}{Rd} & \multicolumn{6}{c|}{16} \ \hline 1 & 1 & 1 & \multicolumn{4}{c|}{} & \multicolumn{4}{c|}{} & 1 & 1 & 1 & 0 & 1 & \multicolumn{2}{c|}{} & \multicolumn{4}{c|}{} & \multicolumn{6}{c|}{} \ \hline \multicolumn{2}{|c|}{15} & \multicolumn{2}{c|}{12} & \multicolumn{2}{c|}{11} & \multicolumn{10}{c|}{disp12} & \multicolumn{12}{c|}{0} \ \hline 1 & 0 & 0 & 0 & \multicolumn{2}{c|}{} & \multicolumn{10}{c|}{} & \multicolumn{12}{c|}{} \ \hline \end{tabular}

32000D-04/2011 ATMEL® 203

LSL – Logical Shift Left

Description

Shifts all bits in a register the amount of bits specified to the left. The shift amount can reside in a register or be specified as an immediate. Zeros are shifted into the LSBs. The last bit that is shifted out is placed in C.

Operation:

I. Rd \leftarrow LSL(Rx, Ry[4:0]); II. Rd \leftarrow LSL(Rd, sa5); III. Rd \leftarrow LSL(Rs, sa5);

Syntax:

I. Isl Rd, Rx, Ry II. Isl Rd, sa III. Isl Rd, Rs, sa

Operands:

I. {d, x, y} \in {0, 1, ..., 15} II. d \in {0, 1, ..., 15} sa \in {0, 1, ..., 31} III. {d,s} \in {0, 1, ..., 15} sa \in {0, 1, ..., 31}

Status Flags:

Format I: Shamt = Ry[4:0], Op = Rx Format II: Shamt = sa5, Op = Rd Format III: Shamt = sa5, Op = Rs Q: Not affected V: Not affected N: N \leftarrow RES[31] Z: Z \leftarrow (RES[31:0] == 0) C: if Shamt != 0 C \leftarrow Op[32-Shamt] else C \leftarrow 0

Opcode:

204 AVR32 32000D–04/2011

AVR32

Format I: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 12 11 4 3 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | Rd |

Format II: 15 13 12 9 8 5 4 3 0 | 1 | 0 | 1 | Bit[4:1] | 1 | 0 | 1 | 1 | Bit[0] | Rd |

Format III: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rs | 0 | 0 | 0 | 0 | 0 | Rd | 15 12 11 8 7 5 4 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | sa5 |

32000D–04/2011 ATMEL® 205

LSR – Logical Shift Right

Description

Shifts all bits in a register the amount specified to the right. The shift amount may be specified by a register or an immediate. Zeros are shifted into the MSB.

Operation:

I. Rd \leftarrow LSR(Rx, Ry[4:0]); II. Rd \leftarrow LSR(Rd, sa5); III. Rd \leftarrow LSR(Rs, sa5);

Syntax:

I. Isr Rd, Rx, Ry II. Isr Rd, sa III. Isr Rd, Rs, sa

Operands:

I. {d, x, y} \in {0, 1, ..., 15} II. d \in {0, 1, ..., 15} sa \in {0, 1, ..., 31} III. {d,s} \in {0, 1, ..., 15} sa \in {0, 1, ..., 31}

Status Flags:

Format I: Shamt = Ry[4:0], Op = Rx Format II: Shamt = sa5, Op = Rd Format III: Shamt = sa5, Op = Rs

Q: Not affected V: Not affected N: N \leftarrow RES[31] Z: Z \leftarrow (RES[31:0] == 0) C: if Shamt != 0 C \leftarrow Op[Shamt-1] else C \leftarrow 0

206 AVR32 32000D–04/2011

Opcode:

Format I: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 12 11 4 3 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | Rd |

Format II: 15 13 12 9 8 5 4 3 0 | 1 | 0 | 1 | Bit[4:0] | 1 | 1 | 0 | 0 | Bit[0]| Rd |

Format III: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rs | 0 | 0 | 0 | 0 | 0 | Rd | 15 12 11 8 7 5 4 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | sa5 |

32000D-04/2011 ATMEL 207

MAC – Multiply Accumulate

Description Performs a Multiply-Accumulate operation and stores the result into the destination register.

Operation: I. Rd \leftarrow (Rx × Ry) + Rd;

Syntax: I. mac Rd, Rx, Ry

Operands: {d, x, y} \in {0, 1, ..., 15}

Status Flags Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 12 11 4 3 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | Rd |

208 AVR32 32000D–04/2011

MACHH.D – Multiply Halfwords and Accumulate in Doubleword

Description Multiplies the two halfword registers specified and adds the result to the specified doubleword-register. Only the 48 highest of the 64 possible bits in the doubleword accumulator are used. The 16 lowest bits are cleared. The halfword registers are selected as either the high or low part of the operand registers.

Operation: I. If (Rx-part == t) then operand1 = SE(Rx[31:16]) else operand1 = SE(Rx[15:0]); If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]); (Rd+1:Rd)[63:16] \leftarrow (operand1 × operand2)[31:0] + (Rd+1:Rd)[63:16]; Rd[15:0] \leftarrow 0;

Syntax: I. machh.d Rd, Rx:, Ry:

Operands: I. d \in {0, 2, 4, ..., 14} {x, y} \in {0, 1, ..., 15} part \in {t,b}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Example: machh.d R10, R2:t, R3:b will perform (R11 : R10)[63:16] \leftarrow ( SE(R2[31:16]) × SE(R3[15:0]) ) + (R11 : R10)[63:16] R10[15:0] \leftarrow 0

32000D–04/2011 ATMEL 209

MACHH.W – Multiply Halfwords and Accumulate in Word

Description

Multiplies the two halfword registers specified and adds the result to the specified word-register. The halfword registers are selected as either the high or low part of the operand registers.

Operation:

I. If (Rx-part == t) then operand1 = SE(Rx[31:16]) else operand1 = SE(Rx[15:0]); If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]); Rd \leftarrow (operand1 × operand2) + Rd;

Syntax:

I. machh.w Rd, Rx:, Ry:

Operands:

I. {d, x, y} \in {0, 1, ..., 15} part \in {t,b}

Status Flags:

Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \multicolumn{1}{c}{31} & \multicolumn{3}{c}{29} & \multicolumn{4}{c}{28} & \multicolumn{3}{c}{25} & \multicolumn{1}{c}{24} & \multicolumn{5}{c}{20} & \multicolumn{1}{c}{19} & \multicolumn{4}{c}{16} \ \hline 1 & 1 & 1 & \multicolumn{4}{c|}{Rx} & \multicolumn{3}{c|}{} & 0 & 0 & 0 & 0 & 0 & \multicolumn{1}{c|}{} & \multicolumn{4}{c}{Ry} \ \hline \end{tabular}

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \multicolumn{2}{c}{15} & \multicolumn{2}{c}{12} & \multicolumn{1}{c}{11} & \multicolumn{3}{c}{8} & \multicolumn{1}{c}{7} & \multicolumn{1}{c}{6} & \multicolumn{1}{c}{5} & \multicolumn{1}{c}{4} & \multicolumn{1}{c}{3} & \multicolumn{4}{c}{0} \ \hline 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & X & Y & \multicolumn{4}{c}{Rd} \ \hline \end{tabular}

Example:

machh.w R10, R2:t, R3:b will perform R10 \leftarrow ( SE(R2[31:16]) × SE(R3[15:0]) ) + R10

MACS.D – Multiply Accumulate Signed

Description Performs a Multiply-Accumulate operation with signed numbers and stores the result into the destination registers.

Operation: I. acc \leftarrow (Rd+1:Rd); prod \leftarrow (Rx × Ry); res \leftarrow prod + acc; (Rd+1:Rd) \leftarrow res;

Syntax: I. macs.d Rd, Rx, Ry

Operands: I. d \in {0, 2, 4, ..., 14} {x, y} \in {0, 1, ..., 15}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 12 11 4 3 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | Rd |

32000D–04/2011 ATMEL® 211

MACSATHH.W – Multiply-Accumulate Halfwords with Saturation into Word

Architecture revision:

Description

Multiplies the two halfword registers specified, shifts the results one position to the left and stores the result as a temporary word-sized product. If the two operands equals -1, the product is saturated to the largest positive 32-bit fractional number. The halfword registers are selected as either the high or low part of the operand registers. The temporary product is added with saturation to Rd.

Operation:

I. If (Rx-part == t) then operand1 = SE(Rx[31:16]) else operand1 = SE(Rx[15:0]); If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]); If (operand1 == operand2 == 0x8000) product ← 0x7FFF_FFFF; else product ← (operand1 × operand2) << 1; Rd ← Sat(product + Rd);

Syntax:

I. macsathh.w Rd, Rx:<part>, Ry:<part>

Operands:

I. {d, x, y} ∈ {0, 1, ..., 15} part ∈ {t,b}

Status Flags:

• Q: Set if saturation occurred, or if the accumulation overflows, or previously set.
• V: Not affected.
• N: Not affected.
• Z: Not affected.
• C: Not affected.

Opcode:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 12 11 8 7 6 5 4 3 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | X | Y | Rd |

Example:

macsathh.w R10, R2:t, R3:b will perform R10 ← Sat (Sat(( SE(R2[31:16]) × SE(R3[15:0]) ) << 1) + R10)

MACU.D – Multiply Accumulate Unsigned

Description Performs a Multiply-Accumulate operation with unsigned numbers and stores the result into the destination registers.

Operation: I. acc \leftarrow (Rd+1:Rd); prod \leftarrow (Rx × Ry); res \leftarrow prod + acc; (Rd+1:Rd) \leftarrow res;

Syntax: I. macu.d Rd, Rx, Ry

Operands: I. d \in {0, 2, 4, ..., 14} {x, y} \in {0, 1, ..., 15}

Status Flags Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 12 11 4 3 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | Rd |

32000D–04/2011 ATMEL® 213

MACWH.D – Multiply Word with Halfword and Accumulate in Doubleword

Architecture revision:

Description

Multiplies the word and halfword register specified and adds the result to the specified doubleword-register. The halfword register is selected as either the high or low part of Ry. Only the 48 highest of the 64 possible bits in the doubleword accumulator are used. The 16 lowest bits are cleared.

Operation:

I. operand1 = Rx; If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]); (Rd+1:Rd)[63:16] ← (operand1 × operand2)[47:0] + (Rd+1:Rd)[63:16]; Rd[15:0] ← 0;

Syntax:

I. macwh.d Rd, Rx, Ry:

Operands:

I. d ∈ {0, 2, ..., 14} {x, y} ∈ {0, 1, ..., 15} part ∈ {t,b}

Status Flags:

• Q: Not affected.
• V: Not affected.
• N: Not affected.
• Z: Not affected.
• C: Not affected.

Opcode:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 12 11 8 7 5 4 3 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | Y | Rd |

Example:

macwh.d R10, R2, R3:b will perform (R11:R10)[63:16] ← (R2 × SE(R3[15:0])) + (R11:R10)[63:16] R10[15:0] ← 0

AVR32

MAX – Return Maximum Value

Description Sets Rd equal to the signed maximum of Rx and Ry.

Operation: I. If Rx > Ry Rd \leftarrow Rx; else Rd \leftarrow Ry;

Syntax: I. max Rd, Rx, Ry

Operands: d, x, y \in {0, 1, ..., 15}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 31 & & 29 & 28 & & & & & 25 & 24 & & & & & & & 20 & 19 & & & & 16 & & & & & & & & & & \ \hline 1 & 1 & 1 & \multicolumn{5}{c|}{Rx} & \multicolumn{5}{c|}{0 0 0 0 0} & \multicolumn{5}{c|}{Ry} & & & & & & & & & & & & & \ \hline \end{tabular}

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & & & & 12 & 11 & & & & & & & & & & & 4 & 3 & & & & 0 & & & & & & & & & & \ \hline 0 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & \multicolumn{9}{c|}{Rd} & & & & & & & & & & & & & \ \hline \end{tabular}

32000D-04/2011 ATMEL 215

MCALL – Subroutine Call

Description Subroutine call to a call destination specified in a location residing in memory.

Operation: I. LR ← PC + 4 PC ← *((Rp & 0xFFFFFFFF) + (SE(disp16) << 2))

Syntax: I. mcall Rp[disp]

Operands: p ∈ {0, 1, ..., 15} disp ∈ {-131072, -131068,..., 131068}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: 31 29 28 20 19 16 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Rp | 15 0 | disp16 |

216 AVR32 32000D–04/2011

MEMC – Clear bit in memory

Description Performs a read-modify-write operation to clear an arbitrary bit in memory. The word to modify is pointed to by a signed 17-bit address. This allows the instruction to address the upper 64KB and lower 64KB of memory. This instruction is part of the optional RMW instruction set.

Operation: l. *(SE(imm15<<2)[bp5]) \leftarrow 0

Syntax: l. memc imm, bp5

Operands: bp5 \in {0, 1, ..., 31} imm \in {-65536, -65532,..., 65532}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: 32000D–04/2011 ATMEL 217

MEMS – Set bit in memory

Description Performs a read-modify-write operation to set an arbitrary bit in memory. The word to modify is pointed to by a signed 17-bit address. This allows the instruction to address the upper 64KB and lower 64KB of memory. This instruction is part of the optional RMW instruction set.

Operation: I. *(SE(imm15<<2)[bp5]) \leftarrow 1

Syntax: I. mems imm, bp5

Operands: bp5 \in {0, 1, ..., 31} imm \in {-65536, -65532,..., 65532}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

218 AVR32 32000D-04/2011

MEMT – Toggle bit in memory

Description Performs a read-modify-write operation to toggle an arbitrary bit in memory. The word to modify is pointed to by a signed 17-bit address. This allows the instruction to address the upper 64KB and lower 64KB of memory. This instruction is part of the optional RMW instruction set.

Operation: I. *(SE(imm15<<2)[bp5]) \leftarrow \neg *(SE(k15<<2)[bp5])

Syntax: I. memt imm, bp5

Operands: bp5 \in \0, 1, ..., 31
imm \in -65536, -65532,..., 65532\

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: 31 20 19 16 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | | | bp5[4:1] | 15 14 0 | b5[0] | | | | | | | | | | | | | | | imm15 |

32000D–04/2011 ATMEL® 219

ATME

MFDR – Move from Debug Register

Description The instruction copies the value in the specified debug register to the specified register in the register file. Note that special timing concerns must be considered when operating on the debug registers, see the Pipeline Chapter for details.

Operation: I. Rd \leftarrow DebugRegister[DebugRegisterAddress << 2];

Syntax: I. mfdr Rd, DebugRegisterNo

Operands: I. DebugRegisterNo \in {0, 4, 8, ..., 1020}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Note: Debug registers are implementation defined. If accessing a debug register that does not exist, the result is UNDEFINED.

This instruction can only be executed in a privileged mode. Execution from any other mode will trigger a Privilege Violation exception.

220 AVR32 32000D-04/2011