Atmel AVR32 user guide: MVCR.{D,W} – Move Coprocessor Register to Register file

MVCR.{D,W} – Move Coprocessor Register to Register file

Description

Addresses a coprocessor and moves the specified registers into the register file.

Operation:

I. (Rd+1:Rd) ← CP#(CRs+1:CRs); II. Rd ← CP#(CRs);

Syntax:

I. mvcr.d CP#, Rd, CRs II. mvcr.w CP#, Rd, CRs

Operands:

I. # ∈ {0, 1, ..., 7} {d, s} ∈ {0, 2, 4, ..., 14} II. # ∈ {0, 1, ..., 7} {d, s} ∈ {0, 1, ..., 15}

Status Flags:

Q: Not affected V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode:

Format I:

Format II:

Example: mvcr.d CP2, R0, CR2

246 AVR32 32000D-04/2011

MVRC.{D,W} – Move Register file Register to Coprocessor Register

Description Moves the specified register into the addressed coprocessor.

Operation: I. CP#(CRd+1:CRd) \leftarrow Rs+1:Rs; II. CP#(CRd) \leftarrow Rs;

Syntax: I. mvrc.d CP#, CRd, Rs II. mvrc.w CP#, CRd, Rs

Operands: I. # \in {0, 1, ..., 7} {d, s} \in {0, 2, 4, ..., 14} II. # \in {0, 1, ..., 7} {d, s} \in {0, 1, ..., 15}

Status Flags: Q: Not affected V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode: Format I: Format II:

Example: mvrc.d CP2, CR0, R2

32000D-04/2011 ATMEL 247

ATMEl

NEG – Two’s Complement

Description Perform a two’s complement of specified register.

Operation: I. Rd \leftarrow 0 -Rd;

Syntax: I. neg Rd

Operands: I. d \in {0, 1, ..., 15}

Status Flags: Q: Not affected V: V \leftarrow Rd[31] \wedge RES[31] N: N \leftarrow RES[31] Z: Z \leftarrow (RES[31:0] == 0) C: C \leftarrow Rd[31] \vee RES[31]

Opcode:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & & 13 & 12 & & & & 9 & 8 & & & & 4 & 3 & & 0 \ \hline 0 & 1 & 0 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 1 & 1 & \multicolumn{4}{c|}{Rd} \ \hline \end{tabular}

248 AVR32 32000D–04/2011

NOP – No Operation

Description Special instructions for "no operation" that does not create data depencencies in the pipeline

Operation: I. none

Syntax: I. nop

Operands: I. none

Status Flags: Q: Not affected V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode:

32000D–04/2011 ATMEL® 249

OR – Logical OR with optional logical shift

Description Performs a bitwise logical OR between the specified registers and stores the result in the destination register.

Operation: I. Rd \leftarrow Rd \vee Rs; II. Rd \leftarrow Rx \vee (Ry << sa5); III. Rd \leftarrow Rx \vee (Ry >> sa5);

Syntax: I. or Rd, Rs II. or Rd, Rx, Ry << sa III. or Rd, Rx, Ry >> sa

Operands: I. {d, s} \in {0, 1, ..., 15} II, III. {d, x, y} \in {0, 1, ..., 15} sa \in {0, 1, ..., 31}

Status Flags: Q: Not affected. V: Not affected. N: N \leftarrow RES[31] Z: Z \leftarrow (RES[31:0] == 0) C: Not affected.

Opcode: Format I:

• \begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c ........ } \hline 15 & 13 & 12 & \multicolumn{8}{c|}{9} & 8 & \multicolumn{5}{c|}{4} & 3 & \multicolumn{7}{c|}{0} \ \hline 0 & 0 & 0 & \multicolumn{8}{c|}{Rs} & 0 & 0 & 1 & 0 & 0 & \multicolumn{7}{c|}{Rd} \ \hline \end{tabular}

Format II:

• \begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c| ........ } \hline 31 & 29 & 28 & \multicolumn{6}{c|}{25} & 24 & \multicolumn{5}{c|}{20} & 19 & \multicolumn{7}{c|}{16} \ \hline 1 & 1 & 1 & \multicolumn{6}{c|}{Rx} & 1 & 1 & 1 & 1 & 0 & \multicolumn{7}{c|}{Ry} \ \hline 15 & \multicolumn{7}{c|}{9} & 8 & \multicolumn{5}{c|}{4} & 3 & \multicolumn{7}{c|}{0} \ \hline 0 & 0 & 0 & 1 & 0 & 0 & 0 & \multicolumn{5}{c|}{sa5} & \multicolumn{7}{c|}{Rd} \ \hline \end{tabular}

250 AVR32 32000D-04/2011

Format III:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 31 & & 29 & 28 & & & & & & & 25 & 24 & & & & & & & & & 20 & 19 & & & & & & & & & 16 \ \hline 1 & & 1 & 1 & \multicolumn{4}{c|}{Rx} & & & 1 & 1 & 1 & 1 & 1 & 0 & \multicolumn{4}{c|}{Ry} & & & & & & & & & & \ \hline 15 & & & & & & & & & & 9 & 8 & & & & & & & & & 4 & 3 & & & & & & & & & 0 \ \hline 0 & & 0 & 0 & 1 & 0 & 0 & 1 & \multicolumn{5}{c|}{sa5} & & & & & & & & Rd & & & & & & & & & \ \hline \end{tabular}

32000D-04/2011 ATMEL 251

OR{cond4} – Conditional logical OR

Architecture revision 2 and higher.

Description Performs a bitwise logical OR between the specified registers and stores the result in the destination register.

Operation:

1. if ( cond4) Rd ← Rx ∨ Ry;

Syntax:

1. or{cond4} Rd, Rx, Ry

Operands:

1. {d, x, y} ∈ {0, 1, ..., 15} cond4 ∈ {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | | | Rx | | | | | 1 | 1 | 1 | 0 | 1 | | | | | Ry | | | | 15 12 11 8 7 0 | 1 | 1 | 1 | 0 | | | | cond4 | | | | 0 | 0 | 1 | 1 | | | | | Rd | | | |

252 AVR32 32000D–04/2011

ORH, ORL – Logical OR into high or low half of register

Description Performs a bitwise logical OR between the high or low word in the specified register and a constant. The result is stored in the destination register.

Operation: I. Rd[31:16] ← Rd[31:16] ∨ imm16; II. Rd[15:0] ← Rd[15:0] ∨ imm16;

Syntax: I. orh Rd, imm II. orl Rd, imm

Operands: I, II. d ∈ {0, 1, ..., 15} imm ∈ {0, 1, ..., 65535}

Status Flags: Q: Not affected V: Not affected N: N ← RES[31] Z: Z ← (RES[31:0] == 0) C: Not affected

Opcode

Format I: Format II:

32000D–04/2011 ATMEL® 253

AMEL®

PABS.{SB/SH} – Packed absolute value

Description

Compute the absolute values of four packed signed bytes (pabs.sb) or two packed signed half-words (pabs.sh) from the source register and store the results as packed bytes or halfwords in the destination register.

Operation:

I. Rd[31:24] \leftarrow | Rs[31:24] |; Rd[23:16] \leftarrow | Rs[23:16] |; Rd[15:8] \leftarrow | Rs[15:8] |; Rd[7:0] \leftarrow | Rs[7:0] |; II. Rd[31:16] \leftarrow | Rs[31:16] |; Rd[15:0] \leftarrow | Rs[15:0] |;

Syntax:

I. pabs.sb Rd, Rs II. pabs.sh Rd, Rs

Operands:

I, II. {d, s} \in {0, 1, ..., 15}

Status Flags:

Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

Format I: Format II:

254 AVR32 32000D–04/2011

PACKSH.{UB/SB} – Pack Signed Halfwords to Bytes

Description Pack the four signed halfwords located in the two source registers into four bytes in the destination register. Each of the signed halfwords are saturated to unsigned (packsh.ub) or signed bytes (packsh.sb).

Operation: I. Rd[31:24] ← SATSU(Rx[31:16], 8); Rd[23:16] ← SATSU(Rx[15:0], 8); Rd[15:8] ← SATSU(Ry[31:16], 8); Rd[7:0] ← SATSU(Ry[15:0], 8); II. Rd[31:24] ← SATS(Rx[31:16], 8); Rd[23:16] ← SATS(Rx[15:0], 8); Rd[15:8] ← SATS(Ry[31:16], 8); Rd[7:0] ← SATS(Ry[15:0], 8);

Syntax: I. packsh.ub Rd, Rx, Ry II. packsh.sb Rd, Rx, Ry

Operands: I, II. {d, x, y} ∈ {0, 1, ..., 15}

Status Flags: Q: Flag set if saturation occured in one or more of the partial operations. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: Format II:

32000D-04/2011 ATMEL 255

256 AVR32 32000D–04/2011

AVR32

PACKW.SH – Pack Words to Signed Halfwords

Description Pack the two words given in the source registers into two halfwords in the destination register. Each of the words are saturated to signed halfwords before being packed.

Operation: I. Rd[31:16] \leftarrow SATS(Rx, 16); Rd[15:0] \leftarrow SATS(Ry, 16);

Syntax: I. packw.sh Rd, Rx, Ry

Operands: I. {d, x, y} \in {0, 1, ..., 15}

Status Flags: Q: Flag set if saturation occured in one or more of the partial operations. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 4 3 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | Rd |

32000D-04/2011 ATMEL 257

PADD.{B/H} – Packed Addition

Description

Perform addition of four pairs of packed bytes (padd.b) or two pairs of halfwords (padd.h). Upon overflow any additional bits are discarded and the result is wrapped around.

Operation:

I. Rd[31:24] \leftarrow Rx[31:24] + Ry[31:24]; Rd[23:16] \leftarrow Rx[23:16] + Ry[23:16]; Rd[15:8] \leftarrow Rx[15:8] + Ry[15:8]; Rd[7:0] \leftarrow Rx[7:0] + Ry[7:0]; II. Rd[31:16] \leftarrow Rx[31:16] + Ry[31:16]; Rd[15:0] \leftarrow Rx[15:0] + Ry[15:0];

Syntax:

I. padd.b Rd, Rx, Ry II. padd.h Rd, Rx, Ry

Operands:

I, II. {d, x, y} \in {0, 1, ..., 15}

Status Flags:

Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

Format I: Format II:

258 AVR32 32000D-04/2011

AVR32

PADDH.{UB/SH} – Packed Addition with Halving

Description Perform addition of four pairs of packed unsigned bytes (paddh.ub) or two pairs of packed signed halfwords (paddh.sh) with a halving of the result to prevent any overflows from occuring.

Operation: I. Rd[31:24] \leftarrow LSR(ZE(Rx[31:24], 9) + ZE(Ry[31:24], 9), 1); Rd[23:16] \leftarrow LSR(ZE(Rx[23:16], 9) + ZE(Ry[23:16], 9), 1); Rd[15:8] \leftarrow LSR(ZE(Rx[15:8], 9) + ZE(Ry[15:8], 9), 1); Rd[7:0] \leftarrow LSR(ZE(Rx[7:0], 9) + ZE(Ry[7:0], 9), 1); II. Rd[31:16] \leftarrow ASR(SE(Rx[31:16], 17) + SE(Ry[31:16], 17), 1); Rd[15:0] \leftarrow ASR(SE(Rx[15:0], 17) + SE(Ry[15:0], 17), 1);

Syntax: I. paddh.ub Rd, Rx, Ry II. paddh.sh Rd, Rx, Ry

Operands: I, II. {d, x, y} \in {0, 1, ..., 15}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: Format II:

32000D-04/2011 ATMEL® 259

PADDS.{UB/SB/UH/SH} – Packed Addition with Saturation

Description

Perform addition of four pairs of packed bytes or two pairs of halfwords. The result is saturated to either unsigned bytes (padds.ub), signed bytes (padds.sb), unsigned halfwords (padds.uh) or signed halfwords (padds.sh).

Operation:

I. Rd[31:24] \leftarrow SATU(ZE(Rx[31:24], 9) + ZE(Ry[31:24], 9), 8); Rd[23:16] \leftarrow SATU(ZE(Rx[23:16], 9) + ZE(Ry[23:16], 9), 8); Rd[15:8] \leftarrow SATU(ZE(Rx[15:8], 9) + ZE(Ry[15:8], 9), 8); Rd[7:0] \leftarrow SATU(ZE(Rx[7:0], 9) + ZE(Ry[7:0], 9), 8); II. Rd[31:24] \leftarrow SATS(SE(Rx[31:24], 9) + SE(Ry[31:24], 9), 8); Rd[23:16] \leftarrow SATS(SE(Rx[23:16], 9) + SE(Ry[23:16], 9), 8); Rd[15:8] \leftarrow SATS(SE(Rx[15:8], 9) + SE(Ry[15:8], 9), 8); Rd[7:0] \leftarrow SATS(SE(Rx[7:0], 9) + SE(Ry[7:0], 9), 8); III. Rd[31:16] \leftarrow SATU(ZE(Rx[31:16], 17) + ZE(Ry[31:16], 17), 16); Rd[15:0] \leftarrow SATU(ZE(Rx[15:0], 17) + ZE(Ry[15:0], 17), 16); IV. Rd[31:16] \leftarrow SATS(SE(Rx[31:16], 17) + SE(Ry[31:16], 17), 16); Rd[15:0] \leftarrow SATS(SE(Rx[15:0], 17) + SE(Ry[15:0], 17), 16);

Syntax:

I. padds.ub Rd, Rx, Ry II. padds.sb Rd, Rx, Ry III. padds.uh Rd, Rx, Ry IV. padds.sh Rd, Rx, Ry

Operands:

I, II, III, IV.{d, x, y} \in {0, 1, ..., 15}

Status Flags:

Q: Flag set if saturation occured in one or more of the partial operations. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

260 AVR32 32000D-04/2011

AVR32

Format I: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 4 3 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | Rd |

Format II: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 4 3 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | Rd |

Format III: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 4 3 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Rd |

Format IV: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 4 3 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Rd |

32000D–04/2011 261

PADDSUB.H – Packed Halfword Addition and Subtraction

Description

Perform an addition and subtraction on the same halfword operands which are selected from the source registers. The two halfword results are packed into the destination register without performing any saturation.

Operation:

I. If (Rx-part == t) then operand1 = Rx[31:16] else operand1 = Rx[15:0]; If (Ry-part == t) then operand2 = Ry[31:16] else operand2 = Ry[15:0]; Rd[31:16] \leftarrow operand1 + operand2; Rd[15:0] \leftarrow operand1 - operand2;

Syntax:

I. paddsub.h Rd, Rx:, Ry:

Operands:

I. {d, x, y} \in {0, 1, ..., 15} part \in {t,b}

Status Flags:

Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

Format I: \begin{tabular}{|c c c|c c c c c|c c c c c|c c c|c c c c c c c c c|} \multicolumn{15}{l}{31 \hspace{2.5em} 29 \hspace{1.5em} 28 \hspace{4em} 25 \hspace{1.5em} 24 \hspace{4em} 20 \hspace{1.5em} 19 \hspace{4em} 16} \ \hline 1 & 1 & 1 & \multicolumn{3}{c|}{Rx} & 0 & 0 & 0 & 0 & 0 & \multicolumn{3}{c|}{Ry} \ \hline \end{tabular}

\begin{tabular}{|c c c|c c c c c|c c|c c c c c c c c c|} \multicolumn{15}{l}{15 \hspace{4em} 6 \hspace{1.5em} 5 \hspace{1.5em} 4 \hspace{1.5em} 3 \hspace{4em} 0} \ \hline 0 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & X & Y & \multicolumn{7}{c|}{Rd} \ \hline \end{tabular}

262 AVR32 32000D-04/2011

AVR32

PADDSUBH.SH – Packed Halfword Addition and Subtraction with Halving

Description

Perform an addition and subtraction on the same signed halfword operands which are selected from the source registers. The halfword results are halved in order to prevent any overflows from occuring

Operation:

I. If (Rx-part == t) then operand1 = Rx[31:16] else operand1 = Rx[15:0]; If (Ry-part == t) then operand2 = Ry[31:16] else operand2 = Ry[15:0]; Rd[31:16] \leftarrow ASR(SE(operand1, 17) + SE(operand2, 17), 1); Rd[15:0] \leftarrow ASR(SE(operand1, 17) - SE(operand2, 17), 1);

Syntax:

I. paddsubh.sh Rd, Rx:, Ry:

Operands:

I. {d, x, y} \in {0, 1, ..., 15} part \in {t,b}

Status Flags:

Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

Format I:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | | | | Rx | | | | | 0 | 0 | 0 | 0 | 0 | | | | | | | Ry | | | | | 15 6 5 4 3 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | X | Y | | | | | Rd | | | | |

32000D-04/2011 ATMEL 263

PADDSUBS.{UH/SH} – Packed Halfword Addition and Subtraction with Saturation

Architecture revision:

Description

Perform an addition and subtraction on the same halfword operands which are selected from the source registers. The resulting halfwords are saturated to unsigned halfwords (paddsubs.uh) or signed halfwords (paddsubs.sh) and then packed together in the destination register.

Operation:

I.
If (Rx-part == t) then operand1 = Rx[31:16] else operand1 = Rx[15:0];
If (Ry-part == t) then operand2 = Ry[31:16] else operand2 = Ry[15:0];
Rd[31:16] ← SATU(ZE(operand1, 17) + ZE(operand2, 17), 16);
Rd[15:0] ← SATSU(ZE(operand1, 17) - ZE(operand2, 17), 16);

II.
If (Rx-part == t) then operand1 = Rx[31:16] else operand1 = Rx[15:0];
If (Ry-part == t) then operand2 = Ry[31:16] else operand2 = Ry[15:0];
Rd[31:16] ← SATS(SE(operand1, 17) + SE(operand2, 17), 16);
Rd[15:0] ← SATS(SE(operand1, 17) - SE(operand2, 17), 16);

Syntax:

I. paddsubs.uh Rd, Rx:, Ry:
II. paddsubs.sh Rd, Rx:, Ry:

Operands:

I,II. {d, x, y} ∈ {0, 1, ..., 15}
part ∈ {t,b}

Status Flags:

Q: Flag set if saturation occured in one or more of the partial operations.
V: Not affected.
N: Not affected.
Z: Not affected.
C: Not affected.

Opcode:

Format I:

Format II:

31 29 28 25 24 20 19 16 ┌───┬───┬───┬─────────────┬───┬───┬───┬───┬───┬─────────────┬───┬───┬───┐ │ 1 │ 1 │ 1 │ Rx │ 0 │ 0 │ 0 │ 0 │ 0 │ Ry │ │ │ │ └──────┴───┴─────────────┴──────┴──────┴────────────────┴───┴───┴───┘ 15 6 5 4 3 0 ┌──────┬──────┬──────┬──────┬──────┬──────┬──────┬─── │ 0 │ 0 │ 1 │ 0 │ 0 │ 0 │ 0 │ 1 │ 1 │ 0 │ X │ Y │ │ │ Rd│ └───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┘

32000D–04/2011 265

PADDX.H – Packed Halfword Addition with Crossed Operand

Description Add together the top halfword of Rx with the bottom halfword of Ry and the bottom halfword of Rx with the top halfword of Ry. The resulting halfwords are packed together in the destination register without performing any saturation.

Operation: I. Rd[31:16] ← Rx[31:16] + Ry[15:0] ; Rd[15:0] ← Rx[15:0] + Ry[31:16];

Syntax: I. paddx.h Rd, Rx, Ry

Operands: I. {d, x, y} ∈ {0, 1, ..., 15}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: \begin{tabular}{|c c c c c c c c c c c c c c c c|} \hline 31 & & & 29 & 28 & & & & 25 & 24 & & & & & 20 & 19 & & & & 16 \ \hline 1 & 1 & 1 & \multicolumn{4}{c|}{Rx} & \multicolumn{6}{c|}{0 0 0 0 0 0} & \multicolumn{4}{c|}{Ry} \ \hline \end{tabular}

\begin{tabular}{|c c c c c c c c c c c c c c|} \hline 15 & & & & & & & & & & & & 4 & 3 & & & & 0 \ \hline 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & \multicolumn{4}{c|}{Rd} \ \hline \end{tabular}

PADDXH.SH – Packed Signed Halfword Addition with Crossed Operand and Halving

Description Add together the top halfword of Rx with the bottom halfword of Ry and the bottom halfword of Rx with the top halfword of Ry. The resulting halfwords are halved in order to avoid any overflow and then packed together in the destination register.

Operation: I. Rd[31:16] \leftarrow ASR(SE(Rx[31:16], 17) + SE(Ry[15:0], 17), 1); Rd[15:0] \leftarrow ASR(SE(Rx[15:0], 17) + SE(Ry[31:16], 17), 1);

Syntax: I. paddxh.sh Rd, Rx, Ry

Operands: I. {d, x, y} \in {0, 1, ..., 15}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 0 0 0 0 | Ry | 15 4 3 0 | 0 0 1 0 0 0 0 0 1 1 1 0 | Rd |

ATMEL 32000D–04/2011 267

PADDXS.{UH/SH} – Packed Halfword Addition with Crossed Operand and Saturation

Description

Add together the top halfword of Rx with the bottom halfword of Ry and the bottom halfword of Rx with the top halfword of Ry. The resulting halfwords are saturated to unsigned halfwords (paddxh.uh) or signed halfwords (paddxh.sh) and then packed together in the destination register.

Operation:

I. Rd[31:16] \leftarrow SATU(ZE(Rx[31:16], 17) + ZE(Ry[15:0], 17), 16); Rd[15:0] \leftarrow SATU(ZE(Rx[15:0], 17) + ZE(Ry[31:16], 17), 16); II. Rd[31:16] \leftarrow SATS(SE(Rx[31:16], 17) + SE(Ry[15:0], 17), 16); Rd[15:0] \leftarrow SATS(SE(Rx[15:0], 17) + SE(Ry[31:16], 17), 16);

Syntax:

I. paddxs.uh Rd, Rx, Ry II. paddxs.sh Rd, Rx, Ry

Operands:

I, II. {d, x, y} \in {0, 1, ..., 15}

Status Flags:

Q: Flag set if saturation occured in one or more of the partial operations. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

Format I:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \multicolumn{1}{c}{31} & \multicolumn{3}{c}{29} & \multicolumn{1}{c}{28} & \multicolumn{5}{c}{25} & \multicolumn{1}{c}{24} & \multicolumn{5}{c}{20} & \multicolumn{1}{c}{19} & \multicolumn{5}{c}{16} \ \hline 1 & 1 & 1 & \multicolumn{5}{c|}{Rx} & 0 & 0 & 0 & 0 & 0 & \multicolumn{5}{c|}{Ry} \ \hline \multicolumn{1}{c}{15} & \multicolumn{11}{c}{4} & \multicolumn{1}{c}{3} & \multicolumn{4}{c}{0} \ \hline 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & \multicolumn{4}{c|}{Rd} \ \hline \end{tabular}

Format II:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \multicolumn{1}{c}{31} & \multicolumn{3}{c}{29} & \multicolumn{1}{c}{28} & \multicolumn{5}{c}{25} & \multicolumn{1}{c}{24} & \multicolumn{5}{c}{20} & \multicolumn{1}{c}{19} & \multicolumn{5}{c}{16} \ \hline 1 & 1 & 1 & \multicolumn{5}{c|}{Rx} & 0 & 0 & 0 & 0 & 0 & \multicolumn{5}{c|}{Ry} \ \hline \multicolumn{1}{c}{15} & \multicolumn{11}{c}{4} & \multicolumn{1}{c}{3} & \multicolumn{4}{c}{0} \ \hline 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & \multicolumn{4}{c|}{Rd} \ \hline \end{tabular}

AVR32

PASR.{B/H} – Packed Arithmetic Shift Right

Description Perform an arithmetic shift right on each of the packed bytes or halfwords in the source register.

Operation: I. Rd[31:24] \leftarrow ASR(Rs[31:24], sa3); Rd[23:16] \leftarrow ASR(Rs[23:16], sa3); Rd[15:8] \leftarrow ASR(Rs[15:8], sa3); Rd[7:0] \leftarrow ASR(Rs[7:0], sa3); II. Rd[31:16] \leftarrow ASR(Rs[31:16], sa4); Rd[15:0] \leftarrow ASR(Rs[15:0], sa4);

Syntax: I. pasr.b Rd, Rs, sa II. pasr.h Rd, Rs, sa

Operands: I, II. {d, s} \in {0, 1, ..., 15} I. sa \in {0, 1, ..., 7} II. sa \in {0, 1, ..., 15}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: 31 29 28 25 24 19 18 16 | 1 | 1 | 1 | Rs | 0 | 0 | 0 | 0 | 0 | 0 | sa3 | 15 4 3 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | Rd |

32000D–04/2011 ATMEL 269