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8.3.1.13 ITLB Miss Exception

The ITLB Miss exception is generated when no TLB entry matches the instruction memory address, or if the Valid bit in a matching entry is 0.

*(--SPSYS) = PC; *(--SPSYS) = SR; TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] = FAILING_PAGE_NUMBER; TLBEHI[I] = 1; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x50;

8.3.1.14 ITLB Protection Exception

The ITLB Protection exception is generated when the instruction memory access violates the access rights specified by the protection bits of the addressed virtual page.

AVR32

8.3.1.15 Breakpoint Exception

The Breakpoint exception is issued when a breakpoint instruction is executed, or the OCD breakpoint input line to the CPU is asserted, and SREG[DM] is cleared.

An external debugger can optionally assume control of the CPU when the Breakpoint Exception is executed. The debugger can then issue individual instructions to be executed in Debug mode. Debug mode is exited with the retd instruction. This passes control from the debugger back to the CPU, resuming normal execution.

RSR_DBG = SR; RAR_DBG = PC; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[D] = 1; SR[DM] = 1; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x1C;

8.3.1.16 Illegal Opcode

This exception is issued when the core fetches an unknown instruction, or when a coprocessor instruction is not acknowledged. When entering the exception routine, the return address on stack points to the instruction that caused the exception.

(--SP$_{SYS}$) = PC;
(--SP$_{SYS}$) = SR; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x20;

8.3.1.17 Unimplemented Instruction

This exception is issued when the core fetches an instruction supported by the instruction set but not by the current implementation. This allows software implementations of unimplemented instructions. When entering the exception routine, the return address on stack points to the instruction that caused the exception.

(--SP$_{SYS}$) = PC;
(--SP$_{SYS}$) = SR; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x24;

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8.3.1.18 Data Read Address Exception The Data Read Address Error exception is generated if the address of a data memory read has an illegal alignment.

*(--SPSYS) = PC; *(--SPSYS) = SR; TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] = FAILING_PAGE_NUMBER; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x34;

8.3.1.19 Data Write Address Exception The Data Write Address Error exception is generated if the address of a data memory write has an illegal alignment.

*(--SPSYS) = PC; *(--SPSYS) = SR; TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] = FAILING_PAGE_NUMBER; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x38;

8.3.1.20 DTLB Read Miss Exception The DTLB Read Miss exception is generated when no TLB entry matches the data memory address of the current read operation, or if the Valid bit in a matching entry is 0.

*(--SPSYS) = PC; *(--SPSYS) = SR; TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] = FAILING_PAGE_NUMBER; TLBEHI[I] = 0; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x60;

AVR32

8.3.1.21 DTLB Write Miss Exception The DTLB Write Miss exception is generated when no TLB entry matches the data memory address of the current write operation, or if the Valid bit in a matching entry is 0.

8.3.1.22 DTLB Read Protection Exception The DTLB Protection exception is generated when the data memory read violates the access rights specified by the protection bits of the addressed virtual page.

8.3.1.23 DTLB Write Protection Exception The DTLB Protection exception is generated when the data memory write violates the access rights specified by the protection bits of the addressed virtual page.

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ATMEL

8.3.1.24 Privilege Violation Exception

If the application tries to execute privileged instructions, this exception is issued. The complete list of priveleged instructions is shown in Table 8-2 on page 78. When entering the exception routine, the address of the instruction that caused the exception is stored as the stacked return address.

*(--SPSYS) = PC; *(--SPSYS) = SR; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x28;

Table 8-2. List of instructions which can only execute in privileged modes.

AVR32

8.3.1.25 DTLB Modified Exception

The DTLB Modified exception is generated when a data memory write hits a valid TLB entry, but the Dirty bit of the entry is 0. This indicates that the page is not writable.

8.3.1.26 Floating-point Exception

The Floating-point exception is generated when the optional Floating-Point Hardware signals that an IEEE exception occurred, or when another type of error from the floating-point hardware occurred..

*(--SPSYS) = PC; *(--SPSYS) = SR; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x2C;

8.3.1.27 Coprocessor Exception

The Coprocessor exception occurs when the addressed coprocessor does not acknowledge an instruction. This permits software implementation of coprocessors.

*(--SPSYS) = PC; *(--SPSYS) = SR; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x30;

ATMEL

8.3.1.28 Supervisor call

Supervisor calls are signalled by the application code executing a supervisor call (scall) instruction. The scall instruction behaves differently depending on which context it is called from. This allows scall to be called from other contexts than Application.

When the exception routine is finished, execution continues at the instruction following scall. The rets instruction is used to return from supervisor calls.

If ( SR[M2:M0] == {B'000 or B'001} ) *(--SPSYS) = PC; *(--SPSYS) = SR; PC ← EVBA + 0x100; SR[M2:M0] ← B'001; else LRCurrent Context ← PC + 2; PC ← EVBA + 0x100;

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AVR32

8.3.2 Description of events in AVR32B

8.3.2.1 Reset Exception

The Reset exception is generated when the reset input line to the CPU is asserted. The Reset exception can not be masked by any bit. The Reset exception resets all synchronous elements and registers in the CPU pipeline to their default value, and starts execution of instructions at address 0xA000_0000.

SR = reset_value_of_SREG; PC = 0xA000_0000;

All other system registers are reset to their reset value, which may or may not be defined. Refer to the Programming Model chapter for details.

8.3.2.2 OCD Stop CPU Exception

The OCD Stop CPU exception is generated when the OCD Stop CPU input line to the CPU is asserted. The OCD Stop CPU exception can not be masked by any bit. This exception is identical to a non-maskable, high priority breakpoint. Any subsequent operation is controlled by the OCD hardware. The OCD hardware will take control over the CPU and start to feed instructions directly into the pipeline.

RSR_DBG = SR; RAR_DBG = PC; SR[M2:M0] = B'110; SR[R] = 0; SR[J] = 0; SR[D] = 1; SR[DM] = 1; SR[EM] = 1; SR[GM] = 1;

8.3.2.3 Unrecoverable Exception

The Unrecoverable Exception is generated when an exception request is issued when the Exception Mask (EM) bit in the status register is asserted. The Unrecoverable Exception can not be masked by any bit. The Unrecoverable Exception is generated when a condition has occurred that the hardware cannot handle. The system will in most cases have to be restarted if this condition occurs.

RSR_EX = SR; RAR_EX = PC of offending instruction; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x00;

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8.3.2.4 TLB Multiple Hit Exception

TLB Multiple Hit exception is issued when multiple address matches occurs in the TLB, causing an internal inconsistency.

This exception signals a critical error where the hardware is in an undefined state. All interrupts are masked, and PC is loaded with EVBA + 0x04. MMU-related registers are updated with information in order to identify the failing address and the failing TLB if multiple TLBs are present. TLBEHI[ASID] is unchanged after the exception, and therefore identifies the ASID that caused the exception.

RSR_EX = SR; RAR_EX = PC of offending instruction; TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] = FAILING_PAGE_NUMBER; TLBEHI[I] = 0/1, depending on which TLB caused the error; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x04;

8.3.2.5 Bus Error Exception on Data Access

The Bus Error on Data Access exception is generated when the data bus detects an error condition. This exception is caused by events unrelated to the instruction stream, or by data written to the cache write-buffers many cycles ago. Therefore, execution can not be resumed in a safe way after this exception. The value placed in RAR_EX is unrelated to the operation that caused the exception. The exception handler is responsible for performing the appropriate action.

RSR_EX = SR; RAR_EX = PC of first non-issued instruction; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x08;

8.3.2.6 Bus Error Exception on Instruction Fetch

The Bus Error on Instruction Fetch exception is generated when the data bus detects an error condition. This exception is caused by events related to the instruction stream. Therefore, execution can be restarted in a safe way after this exception, assuming that the condition that caused the bus error is dealt with.

RSR_EX = SR; RAR_EX = PC; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1;

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SR[GM] = 1; PC = EVBA + 0x0C;

8.3.2.7 NMI Exception

The NMI exception is generated when the NMI input line to the core is asserted. The NMI exception can not be masked by the SR[GM] bit. However, the core ignores the NMI input line when processing an NMI Exception (the SR[M2:M0] bits are B'111). This guarantees serial execution of NMI Exceptions, and simplifies the NMI hardware and software mechanisms.

Since the NMI exception is unrelated to the instruction stream, the instructions in the pipeline are allowed to complete. After finishing the NMI exception routine, execution should continue at the instruction following the last completed instruction in the instruction stream.

RSR_NMI = SR; RAR_NMI = Address of first noncompleted instruction; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'111; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x10;

8.3.2.8 INT3 Exception

The INT3 exception is generated when the INT3 input line to the core is asserted. The INT3 exception can be masked by the SR[GM] bit, and the SR[I3M] bit. Hardware automatically sets the SR[I3M] bit when accepting an INT3 exception, inhibiting new INT3 requests when processing an INT3 request.

The INT3 Exception handler address is calculated by adding EVBA to an interrupt vector offset specified by an interrupt controller outside the core. The interrupt controller is responsible for providing the correct offset.

Since the INT3 exception is unrelated to the instruction stream, the instructions in the pipeline are allowed to complete. After finishing the INT3 exception routine, execution should continue at the instruction following the last completed instruction in the instruction stream.

RSR_INT3 = SR; RAR_INT3 = Address of first noncompleted instruction; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'101; SR[I3M] = 1; SR[I2M] = 1; SR[I1M] = 1; SR[I0M] = 1; PC = EVBA + INTERRUPT_VECTOR_OFFSET;

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8.3.2.9 INT2 Exception

The INT2 exception is generated when the INT2 input line to the core is asserted. The INT2 exception can be masked by the SR[GM] bit, and the SR[I2M] bit. Hardware automatically sets the SR[I2M] bit when accepting an INT2 exception, inhibiting new INT2 requests when processing an INT2 request.

The INT2 Exception handler address is calculated by adding EVBA to an interrupt vector offset specified by an interrupt controller outside the core. The interrupt controller is responsible for providing the correct offset.

Since the INT2 exception is unrelated to the instruction stream, the instructions in the pipeline are allowed to complete. After finishing the INT2 exception routine, execution should continue at the instruction following the last completed instruction in the instruction stream.

RSR_INT2 = SR; RAR_INT2 = Address of first noncompleted instruction; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'100; SR[I2M] = 1; SR[I1M] = 1; SR[I0M] = 1; PC = EVBA + INTERRUPT_VECTOR_OFFSET;

8.3.2.10 INT1 Exception

The INT1 exception is generated when the INT1 input line to the core is asserted. The INT1 exception can be masked by the SR[GM] bit, and the SR[I1M] bit. Hardware automatically sets the SR[I1M] bit when accepting an INT1 exception, inhibiting new INT1 requests when processing an INT1 request.

The INT1 Exception handler address is calculated by adding EVBA to an interrupt vector offset specified by an interrupt controller outside the core. The interrupt controller is responsible for providing the correct offset.

Since the INT1 exception is unrelated to the instruction stream, the instructions in the pipeline are allowed to complete. After finishing the INT1 exception routine, execution should continue at the instruction following the last completed instruction in the instruction stream.

RSR_INT1 = SR; RAR_INT1 = Address of first noncompleted instruction; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'011; SR[I1M] = 1; SR[I0M] = 1; PC = EVBA + INTERRUPT_VECTOR_OFFSET;

8.3.2.11 INT0 Exception

The INT0 exception is generated when the INT0 input line to the core is asserted. The INT0 exception can be masked by the SR[GM] bit, and the SR[I0M] bit. Hardware automatically sets the SR[I0M] bit when accepting an INT0 exception, inhibiting new INT0 requests when processing an INT0 request.

The INT0 Exception handler address is calculated by adding EVBA to an interrupt vector offset specified by an interrupt controller outside the core. The interrupt controller is responsible for providing the correct offset.

Since the INT0 exception is unrelated to the instruction stream, the instructions in the pipeline are allowed to complete. After finishing the INT0 exception routine, execution should continue at the instruction following the last completed instruction in the instruction stream.

RSR_INT0 = SR; RAR_INT0 = Address of first noncompleted instruction; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'010; SR[I0M] = 1; PC = EVBA + INTERRUPT_VECTOR_OFFSET;

8.3.2.12 Instruction Address Exception

The Instruction Address Error exception is generated if the generated instruction memory address has an illegal alignment.

RSR_EX = SR; RAR_EX = PC; TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] = FAILING_PAGE_NUMBER; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x14;

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8.3.2.13 ITLB Miss Exception

The ITLB Miss exception is generated when no TLB entry matches the instruction memory address, or if the Valid bit in a matching entry is 0.

RSR_EX = SR; RAR_EX = PC; TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] = FAILING_PAGE_NUMBER; TLBEHI[I] = 1; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x50;

8.3.2.14 ITLB Protection Exception

The ITLB Protection exception is generated when the instruction memory access violates the access rights specified by the protection bits of the addressed virtual page.

RSR_EX = SR; RAR_EX = PC; TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] = FAILING_PAGE_NUMBER; TLBEHI[I] = 1; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x18;

8.3.2.15 Breakpoint Exception

The Breakpoint exception is issued when a breakpoint instruction is executed, or the OCD breakpoint input line to the CPU is asserted, and SREG[DM] is cleared.

RSR_DBG = SR; RAR_DBG = PC; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[D] = 1; SR[DM] = 1;

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SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x1C;

8.3.2.16 Illegal Opcode

RSR_EX = SR; RAR_EX = PC; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x20;

8.3.2.17 Unimplemented Instruction

RSR_EX = SR; RAR_EX = PC; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x24;

8.3.2.18 Data Read Address Exception

The Data Read Address Error exception is generated if the address of a data memory read has an illegal alignment.

RSR_EX = SR; RAR_EX = PC; TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] = FAILING_PAGE_NUMBER; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x34;

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8.3.2.19 Data Write Address Exception

The Data Write Address Error exception is generated if the address of a data memory write has an illegal alignment.

RSR_EX = SR; RAR_EX = PC; TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] = FAILING_PAGE_NUMBER; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x38;

8.3.2.20 DTLB Read Miss Exception

The DTLB Read Miss exception is generated when no TLB entry matches the data memory address of the current read operation, or if the Valid bit in a matching entry is 0.

RSR_EX = SR; RAR_EX = PC; TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] = FAILING_PAGE_NUMBER; TLBEHI[I] = 0; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x60;

8.3.2.21 DTLB Write Miss Exception

The DTLB Write Miss exception is generated when no TLB entry matches the data memory address of the current write operation, or if the Valid bit in a matching entry is 0.

RSR_EX = SR; RAR_EX = PC; TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] = FAILING_PAGE_NUMBER; TLBEHI[I] = 0; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x70;

AVR32

8.3.2.22 DTLB Read Protection Exception The DTLB Protection exception is generated when the data memory read violates the access rights specified by the protection bits of the addressed virtual page.

RSR_EX = SR; RAR_EX = PC; TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] = FAILING_PAGE_NUMBER; TLBEHI[I] = 0; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x3C;

8.3.2.23 DTLB Write Protection Exception The DTLB Protection exception is generated when the data memory write violates the access rights specified by the protection bits of the addressed virtual page.

RSR_EX = SR; RAR_EX = PC; TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] = FAILING_PAGE_NUMBER; TLBEHI[I] = 0; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x40;

8.3.2.24 Privilege Violation Exception If the application tries to execute privileged instructions, this exception is issued. The complete list of priveleged instructions is shown in Table 8-2. When entering the exception routine, the address of the instruction that caused the exception is stored as yhe stacked return address.

RSR_EX = SR; RAR_EX = PC; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x28;

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Table 8-3. List of instructions which can only execute in privileged modes.

Privileged Instructions	Comment
csrf - clear status register flag	Privileged only when accessing upper half of status register
cache - perform cache operation
tlbr - read addressed TLB entry into TLBEHI and TLBELO
tlbw - write TLB entry registers into TLB
tlbs - search TLB for entry matching TLBEHI[VPN]
mtsr - move to system register	Unprivileged when accessing JOSP and JECR
mfsr - move from system register	Unprivileged when accessing JOSP and JECR
- move to debug register
mfdr - move from debug register
rete- return from exception
rets - return from supervisor call
retd - return from debug mode
sleep - sleep
ssrf - set status register flag	Privileged only when accessing upper half of status register

8.3.2.25 DTLB Modified Exception

The DTLB Modified exception is generated when a data memory write hits a valid TLB entry, but the Dirty bit of the entry is 0. This indicates that the page is not writable.

RSR_EX = SR; RAR_EX = PC; TLBEAR = FAILING_VIRTUAL_ADDRESS; TLBEHI[VPN] = FAILING_PAGE_NUMBER; TLBEHI[I] = 0; SR[R] = 0; SR[J] = 0; SR[M2:M0] = B'110; SR[EM] = 1; SR[GM] = 1; PC = EVBA + 0x44;

AVR32

8.3.2.26 Floating-point Exception

The Floating-point exception is generated when the optional Floating-Point Hardware signals that an IEEE exception occurred, or when another type of error from the floating-point hardware occurred..

$$ \begin{aligned} & \text{RSR_EX = SR;} \ & \text{RAR_EX = PC;} \ & \text{SR[R] = 0;} \ & \text{SR[J] = 0;} \ & \text{SR[M2:M0] = B'110;} \ & \text{SR[EM] = 1;} \ & \text{SR[GM] = 1;} \ & \text{PC = EVBA + 0x2C;} \end{aligned} $$

8.3.2.27 Coprocessor Exception

The Coprocessor exception occurs when the addressed coprocessor does not acknowledge an instruction. This permits software implementation of coprocessors.

8.3.2.28 Supervisor call

When the exception routine is finished, execution continues at the instruction following scall. The rets instruction is used to return from supervisor calls.

$$ \begin{aligned} & \text{If ( SR[M2:M0] == {B'000 or B'001} )} \ & \quad \text{RAR_SUP} \leftarrow \text{PC + 2;} \ & \quad \text{RSR_SUP} \leftarrow \text{SR;} \ & \quad \text{PC} \leftarrow \text{EVBA + 0x100;} \ & \quad \text{SR[M2:M0]} \leftarrow \text{B'001;} \ & \text{else} \ & \quad \text{LR}_{\text{Current Context}} \leftarrow \text{PC + 2;} \ & \quad \text{PC} \leftarrow \text{EVBA + 0x100;} \end{aligned} $$

8.4 Event priority

Several instructions may be in the pipeline at the same time, and several events may be issued in each pipeline stage. This implies that several pending exceptions may be in the pipeline simultaneously. Priorities must therefore be imposed, ensuring that the correct event is serviced first. The priority scheme obeys the following rules:

If several instructions trigger events, the instruction furthest down the pipeline is serviced first, even if upstream instructions have pending events of higher priority.
If this instruction has several pending events, the event with the highest priority is serviced first. After this event has been serviced, all pending events are cleared and the instruction is restarted.

Details about the timing of events is IMPLEMENTATION DEFINED, and given in the hardware manual for the specific implementation.

8.5 Event handling in secure state

Interrupt and exception handling in AVR32A and AVR32B has been described in the previous chapters. This behavior is modified in the following way when interrupts and exceptions are received in secure state:

• A sscall instruction will set SR[GM]. In secure state, SR[GM] masks both INT0-INT3, and NMI. Clearing SR[GM], INT0-INT3 and NMI will remove the mask of these event sources. INT0-INT3 are still additionally masked by the I0M-I3M bits in the status register.

• sscall has handler address at offset 0x4 relative to the reset handler address.

• Exceptions have a handler address at offset 0x8 relative to the reset handler address.

• NMI has a handler address at offset 0xC relative to the reset handler address.

• BREAKPOINT has a handler address at offset 0x10 relative to the reset handler address.

• INT0-INT3 are not autovectored, but have a common handler address at offset 0x14 relative to the reset handler address.

Note that in the secure state, all exception sources share the same handler address. It is therefore not possible to separate different exception causes when in the secure world. The secure world system must be designed to support this, the most obvious solution is to design the secure software so that exceptions will not arise.

9. AVR32 RISC Instruction Set

9.1 Instruction Set Nomenclature

9.1.1 Registers and Operands

R{d, s, ...} The uppercase ‘R’ denotes a 32-bit (word) register.

Rd The lowercase ‘d’ denotes the destination register number.

Rs The lowercase ‘s’ denotes the source register number.

Rx The lowercase ‘x’ denotes the first source register number for three register operations.

Ry The lowercase ‘y’ denotes the second source register number for three register operations.

Rb The lowercase ‘b’ denotes the base register number for indexed addressing modes.

Ri The lowercase ‘i’ denotes the index register number for indexed addressing modes.

Rp The lowercase ‘p’ denotes the pointer register number.

PC Program Counter, equal to R15

LR Link Register, equal to R14

SP Stack Pointer, equal to R13

Reglist8 Reglist8 ∈ {R0-R3, R4-R7, R8-R9, R10, R11, R12, LR, PC}

Reglist16 Reglist16 ∈ {R0, R1, R2, ..., R12, LR, SP, PC}

ReglistCPH8 ReglistCPH8 ∈ {CR8, CR9, CR10, ..., CR15}

ReglistCPL8 ReglistCPL8 ∈ {CR0, CR1, CR2, ..., CR7}

ReglistCP8 ReglistCPD8 ∈ {CR0-CR1,CR2-CR3,CR4-CR5,CR6-CR7,CR8-CR9, CR10-CR11,CR12-CR13,CR14-CR15}

SysRegName Name of source or destination system register.

cond3 cond3 ∈ {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl}

cond4 cond4 ∈ {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}

disp Displacement

disp:E Displacement of n bits. If the both compact and extended versions of the instruction exists, then use the extended version. The compact version is used by default.

imm Immediate value

imm:E Immediate of n bits. If the both compact and extended versions of the instruction exists, then use the extended version. The compact version is used by default.

sa Shift amount

bp Bit postion

w Width of a bit field

[i] Denotes bit i in a immediate value. Example: imm6[4] denotes bit 4 in an 6-bit immediate value.

[i:j] Denotes bit i to j in an immediate value.

Some instructions access or use doubleword operands. These operands must be placed in two consecutive register addresses where the first register must be an even register. The even register contains the least significant part and the odd register contains the most significant part. This ordering is reversed in comparison with how data is organized in memory (where the most significant part would receive the lowest address) and is intentional.

The programmer is responsible for placing these operands in properly aligned register pairs. This is also specified in the "Operands" section in the detailed description of each instruction. Failure to do so will result in an undefined behaviour.

9.1.2 Operator Symbols

| ^ | Bitwise logical AND operation. | | v | Bitwise logical OR operation. | | ⊗ | Bitwise logical EOR operation. | | ¬ | Bitwise logical NOT operation. | | Sat | Saturate operand |

9.1.3 Operations

9.1.4 Status Register Flags

| C: | Carry / Borrow flag. | | Z: | Zero flag, set if the result of the operation is zero. | | N: | Bit 31 of the result. | | V: | Set if 2's complement overflow occurred. | | Q: | Saturated flag, set if saturation and/or overflow has occurred after some instructions. | | M0: | Mode bit 0 |

94 AVR32 32000D–04/2011

M1: Mode bit 1
M2: Mode bit 2

9.1.5 Data Type Extensions

.d Double (64-bit) operation.
.w Word (32-bit) operation.
.h Halfword (16-bit) operation.
.b Byte operation (8-bit) operation.

9.1.6 Halfword selectors

t Top halfword, bits 31-16.
b Bottom halfword, bits 15-0.

9.1.7 Byte selectors

t Top byte, bits 31-24.
u Upper byte, bits 23-16.
l Lower byte, bits 15-8.
b Bottom byte, bits 7-0.

9.1.8 CPU System Registers

RSR_INT0: Interrupt level 0 Return Status Register.
RSR_INT1: Interrupt level 1 Return Status Register.
RSR_INT2: Interrupt level 2 Return Status Register.
RSR_INT3: Interrupt level 3 Return Status Register.
RSR_EX: Exception Return Status Register.
RSR_NMI: Non maskable interrupt Return Status Register.
RSR_SUP: Supervisor Return Status Register.
RAR_INT0: Interrupt level 0 Return Address Register.
RAR_INT1: Interrupt level 1 Return Address Register.
RAR_INT2: Interrupt level 2 Return Address Register.
RAR_INT3: Interrupt level 3 Return Address Register.
RAR_EX: Exception Return Address Register.
RAR_NMI: Non maskable interrupt Return Address Register.
RAR_SUP: Supervisor Return Address Register.
ACBA: Application Call Base Address register.
EVBA: Exception Vector Base Address register.

9.1.9 Branch conditions

Table 9-1. Branch conditions

Text converted from the manufacturer's document. A □ marks a character that could not be read in the original. Back to the Atmel AVR32 discussions