Atmel AVR32 user guide: 9.2.36 Coprocessor load and store

AVR32

9.2 Instruction Formats

This is an overview of the different instruction formats.

9.2.1 Two Register Instructions

\begin{tabular}{|c|c|c|c|} \hline Opcod & Rs/Rp & Opcode & Rd/Rs \ \hline \end{tabular} 15 \quad 13 \quad 12 \quad 9 \quad 8 \quad 4 \quad 3 \quad 0

9.2.2 Single Register Instructions

\begin{tabular}{|c|c|c|} \hline 0 \quad 1 \quad 0 \quad 1 \quad 1 \quad 1 \quad 0 & Opcode & Rd \ \hline \end{tabular} 15 \quad 13 \quad 12 \quad 9 \quad 8 \quad 4 \quad 3 \quad 0

9.2.3 Return and test

\begin{tabular}{|c|c|c|} \hline 0 \quad 1 \quad 0 \quad 1 \quad 1 \quad 1 \quad 1 \quad Opc & cond4 & Rs/Rd \ \hline \end{tabular} 15 \quad 13 \quad 12 \quad 9 \quad 8 \quad 7 \quad 4 \quad 3 \quad 0

9.2.4 K8 immediate and single register

\begin{tabular}{|c|c|c|} \hline 0 \quad 0 \quad 1 \quad Opc & k8 & Rd \ \hline \end{tabular} 15 \quad 13 \quad 12 \quad 11 \quad 4 \quad 3 \quad 0

9.2.5 SP / PC relative load / store

\begin{tabular}{|c|c|c|} \hline 0 \quad 1 \quad 0 \quad Opcode & k7 & Rd/Rs \ \hline \end{tabular} 15 \quad 13 \quad 12 \quad 11 \quad 10 \quad 4 \quad 3 \quad 0

9.2.6 K5 immediate and single register

\begin{tabular}{|c|c|c|} \hline 0 \quad 1 \quad 0 \quad 1 \quad 1 \quad 0 \quad Opc & k5 & Rd \ \hline \end{tabular} 15 \quad 13 \quad 12 \quad 10 \quad 9 \quad 8 \quad 4 \quad 3 \quad 0

9.2.7 Displacement load with k5 immediate

\begin{tabular}{|c|c|c|} \hline 0 \quad 1 \quad 1 \quad Rp & k5 & Rd \ \hline \end{tabular} 15 \quad 13 \quad 12 \quad 9 \quad 8 \quad 4 \quad 3 \quad 0

9.2.8 Displacement load / store with k3 immediate

\begin{tabular}{|c|c|c|c|} \hline 1 \quad 0 \quad 0 \quad Rp & Opcode & k3 & Rd/Rs \ \hline \end{tabular} 15 \quad 14 \quad 13 \quad 12 \quad 9 \quad 8 \quad 7 \quad 6 \quad 4 \quad 3 \quad 0

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9.2.9 One register and a register pair 15 13 12 9 8 6 5 4 3 1 0 | 1 | 0 | 1 | Rp | 1 | 0 | 0 | Opc | Rd/Rs | Opc |

9.2.10 One register with k8 immediate and cond4 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Opcode | 1 | 1 | 0 | 1 | 1 | Rd | 15 12 11 8 7 0 | 0 | 0 | 0 | 0 | cond4 | k8 |

9.2.11 One register with bit addressing 15 13 12 9 8 5 4 3 0 | 1 | 0 | 1 | Bit[4:1] | Opcode | Bit[0] | Rd |

9.2.12 Short branch 15 13 12 11 4 3 2 0 | 1 | 1 | 0 | 0 | k8 | 0 | cond3 |

9.2.13 Relative jump and call 15 13 12 11 4 3 2 1 0 | 1 | 1 | 0 | 0 | K10[7:0] | 1 | Opc | K10[9:8] |

9.2.14 K8 and no register 15 12 11 4 3 1 0 | 1 | 1 | 0 | 1 | k8/Label | 0 | 0 | 0 | Opc |

9.2.15 Multiple registers (POPM) 15 3 2 0 | 1 | 1 | 0 | 1 | PC LR 12 11 10 9-8 7-4 3-0 k | 0 | 1 | 0 |

9.2.16 Multiple registers (PUSHM) 15 13 12 11 4 3 0 | 1 | 1 | 0 | 1 | PC LR 12 11 10 9-8 7-4 3-0 | 0 | 0 | 1 | 1 |

9.2.17 Status register bit specification 15 11 10 9 8 4 3 0 | 1 | 1 | 0 | 1 | 0 | Opcode | Bit No | 0 | 1 | 0 | 0 |

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9.2.18 Only Opcode 15 9 8 4 3 0 1 1 0 1 0 1 1 Opcode 0 1 0 0

9.2.19 3 registers shifted 31 29 28 25 24 20 19 16 1 1 1 Rb/Rx 0 0 0 0 0 Ry/Ri 15 12 11 8 7 6 5 4 3 0 0 0 0 0 Opcode 0 0 Shift Amount Rd/Rs

9.2.20 3 registers unshifted 31 29 28 25 24 20 19 16 1 1 1 Rx 0 0 0 0 0 Ry 15 12 11 4 3 0 0 0 0 0 Opcode Rd

9.2.21 DSP Halfword Multiply 31 29 28 25 24 20 19 16 1 1 1 Rx 0 0 0 0 0 Ry 15 12 11 8 7 6 5 4 3 0 0 0 0 0 Opcode 0 0 X Y Rd

9.2.22 DSP Word and Halfword Multiply 31 29 28 25 24 20 19 16 1 1 1 Rx 0 0 0 0 0 Ry 15 12 11 8 7 5 4 3 0 0 0 0 0 Opcode 1 0 0 Y Rd

9.2.23 2 register operands with k8 immediate 31 29 28 25 24 20 19 16 1 1 1 Rs 0 0 0 0 0 Rd 15 12 11 8 7 0 0 0 0 1 Opcode k8

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9.2.24 2 register operands with k5 immediate

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rs | 0 | 0 | 0 | 0 | 0 | Rd | 15 12 11 8 7 5 4 0 | 0 | 0 | 0 | 1 | Opcode | 0 | 0 | 0 | k5 |

9.2.25 2 Registers with w5 and o5

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rd | 1 | 1 | 1 | 0 | 1 | Rs | 15 10 9 5 4 0 | Opcode | o5 | w5 |

9.2.26 Coprocessor 0 load and store

31 29 28 26 25 24 20 19 16 | 1 | 1 | 1 | 1 | Opc | 1 | 1 | 0 | 1 | 0 | Rp | 15 13 12 11 8 7 6 0 | k12 [11:8] | CRd/CRs | k12[7:0] |

9.2.27 2 register operands

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rs | 0 | 0 | 0 | 0 | 0 | Rd | 15 12 11 8 7 0 | 0 | 0 | 0 | 1 | Opcode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |

9.2.28 Register operand with K16

31 29 28 20 19 16 | 1 | 1 | 1 | Opcode | Rd/Rp | 15 0 | k16 |

9.2.29 Cache operation

31 20 19 16 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | Rp | 15 0 | Op5 | k11 |

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AVR32

9.2.30 Register or condition code and K21

9.2.31 No register and k21

9.2.32 Two registers and K16

9.2.33 Register, doubleword register and K16

9.2.34 K16 and bit address

9.2.35 Coprocessor Operation

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9.2.36 Coprocessor load and store

9.2.37 Coprocessor load and store multiple registers

9.2.38 Coprocessor load, store and move

9.2.39 Coprocessor load and store with indexed addressing

9.2.40 Register and system register

9.2.41 Sleep and sync

AVR32

9.2.42 Register and bit address

9.2.43 Load and store multiple registers

9.2.44 Register, k12 and halfword select

9.2.45 Register, k12 and byte select

9.2.46 2 Register and k12

9.2.47 ANDL / ANDH

9.2.48 Saturate

9.2.49 3 Registers with k5

9.2.50 2 Registers with k4

9.2.51 2 Registers with cond4

9.2.52 4 Registers with k2

9.2.53 3 Registers with k8 and sa

9.2.54 k3 immediate

AVR32

9.2.55 Address and b5 9.2.56 2 register operands 9.2.57 2 register operands and k3 9.2.58 2 register operands and k4

9.3 Instruction Set Summary

9.3.1 Architecture revision

Unless otherwise noted, all instructions are part of revision 1 of the AVR32 architecture. The following instructions were added in revision 2, none were removed:

• movh Rd, imm • {add, sub, and, or, eor}{cond4}, Rd, Rx, Ry • ld.{sb, ub, sh, uh, w}{cond4} Rd, Rp[disp] • st.{b, h, w}{cond4} Rp[disp], Rs • rsub{cond4} Rd, imm

9.3.2 Arithmetic Operations

Table 9-2. Arithmetic Operations

Table 9-2. Arithmetic Operations (Continued)

9.3.3 Multiplication Operations

Table 9-3. Multiplication Operations

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9.3.4 DSP Operations

Table 9-4. DSP Operations

Table 9-4. DSP Operations (Continued)

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9.3.5 Logic Operations

Table 9-5. Logic Operations

9.3.6 Bit Operations

Table 9-6. Bit Operations

\begin{tabular}{|l|l|l|l|l|l|} \hline Mnemonics & & Operands / Syntax & Description & Operation & Rev \ \hline bfexts & E & Rd, Rs, o5, w5 & Extract and sign-extend the w5 bits in Rs starting at bit-offset o5 to Rd. & See Instruction Set Reference & 1 \ \hline bfextu & E & Rd, Rs, o5, w5 & Extract and zero-extend the w5 bits in Rs starting at bit-offset o5 to Rd. & See Instruction Set Reference & 1 \ \hline bfins & E & Rd, Rs, o5, w5 & Insert the lower w5 bits of Rs in Rd at bit-offset o5. & See Instruction Set Reference & 1 \ \hline bld & E & Rd, bp & Bit load. & C \leftarrow Rd[bp5] Z \leftarrow Rd[bp5] & 1 \ \hline brev & C & Rd & Bit reverse. & Rd[0:31] \leftarrow Rd[31:0] & 1 \ \hline bst & E & Rd, bp & Bit store. & Rd[bp5] \leftarrow C & 1 \ \hline casts.b & C & Rd & Typecast byte to signed word. & Rd \leftarrow SE(Rd[7:0]) & 1 \ \hline casts.h & C & Rd & Typecast halfword to signed word. & Rd \leftarrow SE(Rd[15:0]) & 1 \ \hline castu.b & C & Rd & Typecast byte to unsigned word. & Rd \leftarrow ZE(Rd[7:0]) & 1 \ \hline castu.h & C & Rd & Typecast halfword to unsigned word. & Rd \leftarrow ZE(Rd[15:0]) & 1 \ \hline cbr & C & Rd, bp & Clear bit in register. & Rd[bp5] \leftarrow 0 & 1 \ \hline clz & E & Rd, Rs & Count leading zeros. & See Instruction Set Reference & 1 \ \hline sbr & C & Rd, bp & Set bit in register. & Rd[bp5] \leftarrow 1 & 1 \ \hline swap.b & C & Rd & Swap bytes in register. & Rd[31:24] \leftarrow Rd[7:0], Rd[23:16] \leftarrow Rd[15:8], Rd[15:8] \leftarrow Rd[23:16], Rd[7:0] \leftarrow Rd[31:24] & 1 \ \hline swap.bh & C & Rd & Swap bytes in each halfword. & Rd[31:24] \leftarrow Rd[23:16], Rd[23:16] \leftarrow Rd[31:24], Rd[15:8] \leftarrow Rd[7:0], Rd[7:0] \leftarrow Rd[15:8] & 1 \ \hline swap.h & C & Rd & Swap halfwords in register. & Rd[31:16] \leftarrow Rd[15:0], Rd[15:0] \leftarrow Rd[31:16] & 1 \ \hline \end{tabular}

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9.3.7 Shift Operations

Table 9-7. Operations

9.3.8 Instruction Flow

Table 9-8. Instruction Flow

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9.3.9 Data Transfer

9.3.9.1 Move/Load Immediate operations

Table 9-9. Move/Load Immediate Operations

9.3.9.2 Load/Store operations

Table 9-10. Load/Store Operations

AVR32

Table 9-10. Load/Store Operations (Continued)

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Table 9-10. Load/Store Operations (Continued)

Table 9-10. Load/Store Operations (Continued)

9.3.9.3 Multiple data

Table 9-11. Mutiple data

9.3.10 System/Control

Table 9-12. System/Control

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Table 9-12. System/Control (Continued)

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9.3.11 Coprocessor interface

Table 9-13. Coprocessor Interface

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Table 9-13. Coprocessor Interface (Continued)

9.3.12 Instructions to aid Java execution

Table 9-14. Instructions to aid Java (Card) execution

9.3.13 SIMD Operations

Table 9-15. SIMD Operations

Table 9-15. SIMD Operations (Continued)

9.3.14 Memory read-modify-write instructions

Table 9-16. Memory read-modify-write Instructions

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