Atmel AVR32 user guide: INCJOSP – Increment Java Operand Stack Pointer

INCJOSP – Increment Java Operand Stack Pointer

Architecture revision:

Description

Increment the system register "Java Operand Stack Pointer" with value.

Operation:

I.
if ( JOSP[3:0] + imm < 0 )
  TRAP 4
else if (JOSP[3:0] + imm > 8 )
  TRAP 3
else
  JOSP ← JOSP + imm;

Syntax:

I.  incjosp imm

Operands:

I.  imm ∈ {-4, -3, -2, -1, 1, 2, 3, 4}

Status Flags:

Q:  Not affected
V:  Not affected
N:  Not affected
Z:  Not affected
C:  Not affected

Opcode:

15 13 12 7 6 4 3 0 1 1 0 1 0 1 1 0 1 imm3 0 0 1 1

Note: When trapped, this instruction will destroy R12. It is the programmer’s responsibility to keep the R12value if needed.

172 AVR32 32000D–04/2011

LD.D – Load Doubleword

Description Reads the doubleword memory location specified.

Operation: I. Rd+1:Rd ← *(Rp); Rp ← Rp + 8; II. Rp ← Rp - 8; Rd+1:Rd ← *(Rp); III. Rd+1:Rd ← *(Rp); IV. Rd+1:Rd ← *(Rp + (SE(disp16))); V. Rd+1:Rd ← *(Rb + (Ri << sa2));

Syntax: I. ld.d Rd, Rp++ II. ld.d Rd, --Rp III. ld.d Rd, Rp IV. ld.d Rd, Rp[disp] V. ld.d Rd, Rb[Ri<<sa]

Operands: I-V. d ∈ {0, 2, 4, ..., 14} p, b, i ∈ {0, 1, ..., 15} IV. disp ∈ {-32768, -32767, ..., 32767} V. sa ∈ {0, 1, 2, 3}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: 15 13 12 9 8 6 5 4 3 1 0 | 1 | 0 | 1 | Rp | 1 | 0 | 0 | 0 | 0 | Rd | 1 |

32000D–04/2011 ATMEL® 173

Format II:

Format III:

Format IV:

Format V:

Note:

Format I and II: If Rd = Rp, the result is UNDEFINED.
If Rd = Rp+1, the result is UNDEFINED.

LD.SB – Load Sign-extended Byte

Description Reads the byte memory location specified and sign-extends it.

Operation: I. Rd \leftarrow SE( *(Rp + (SE(displ6))) ); II. Rd \leftarrow SE( *(Rb + (Ri << sa2)) );

Syntax: I. ld.sb Rd, Rp[disp] II. ld.sb Rd, Rb[Ri<<sa]

Operands: I. d, p \in {0, 1, ..., 15} disp \in {-32768, -32767, ..., 32767} II. d, b, i \in {0, 1, ..., 15} sa \in {0, 1, 2, 3}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: Format II:

32000D-04/2011 ATMEL 175

ATME

LD.SB{cond4} – Conditionally Load Sign-extended Byte

Architecture revision 2 and higher.

Description Reads the byte memory location specified and sign-extends it if the given condition is satisfied.

Operation:

1. if (cond4) Rd \leftarrow SE( *(Rp + (ZE(disp9))) );

Syntax:

1. ld.sb{cond4} Rd, Rp[disp]

Operands:

1. d, p \in {0, 1, ..., 15} disp \in {0, 1, ..., 511} cond4 \in {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

176 AVR32 32000D–04/2011

LD.UB – Load Zero-extended Byte

Description Reads the byte memory location specified and zero-extends it.

Operation: I. Rd \leftarrow ZE( *(Rp) ); Rp \leftarrow Rp + 1; II. Rp \leftarrow Rp - 1; Rd \leftarrow ZE( *(Rp) ); III. Rd \leftarrow ZE( *(Rp + (ZE(displ))) ); IV. Rd \leftarrow ZE( *(Rp + (SE(displ6))) ); V. Rd \leftarrow ZE( *(Rb + (Ri << sa2)) );

Syntax: I. ld.ub Rd, Rp++ II. ld.ub Rd, --Rp III. ld.ub Rd, Rp[disp] IV. ld.ub Rd, Rp[disp] V. ld.ub Rd, Rb[Ri<<sa]

Operands: I-V. d, p, b, i \in {0, 1, ..., 15} III. disp \in {0, 1, ..., 7} IV. disp \in {-32768, -32767, ..., 32767} V. sa \in {0, 1, 2, 3}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: 15 13 12 9 8 4 3 0 0 0 0 Rp 1 0 0 1 1 Rd

32000D–04/2011 ATMEL® 177

ATMEl

Format II: 15 13 12 9 8 4 3 0 0 0 0 Rp 1 0 1 1 1 Rd

Format III: 15 13 12 9 8 7 6 4 3 0 0 0 0 Rp 1 1 disp3 Rd

Format IV: 31 29 28 25 24 20 19 16 1 1 1 Rp 1 0 0 1 1 Rd 15 0 disp16

Format V: 31 29 28 25 24 20 19 16 1 1 1 Rb 0 0 0 0 0 Ri 15 12 11 8 7 6 5 4 3 0 0 0 0 0 0 1 1 1 0 0 Shift Amount Rd

Note: Format I and II: If Rd = Rp, the result is UNDEFINED.

178 AVR32 32000D–04/2011

LD.UB{cond4} – Conditionally Load Zero-extended Byte

Architecture revision 2 and higher.

Description Reads the byte memory location specified and zero-extends it if the given condition is satisfied.

Operation: I. if (cond4) Rd ← ZE( *(Rp + (ZE(disp9)) ) );

Syntax: I. ld.ub{cond4} Rd, Rp[disp]

Operands: I. d, p ∈ {0, 1, ..., 15} disp ∈ {0, 1, ..., 511} cond4 ∈ {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

32000D–04/2011 ATMEL® 179

LD.SH – Load Sign-extended Halfword

Description Reads the halfword memory location specified and sign-extends it.

Operation: I. Rd \leftarrow SE( *(Rp) ); Rp \leftarrow Rp + 2; II. Rp \leftarrow Rp - 2; Rd \leftarrow SE( *(Rp) ); III. Rd \leftarrow SE( *(Rp + (ZE(disp3) << 1)) ); IV. Rd \leftarrow SE( *(Rp + (SE(disp16))) ); V. Rd \leftarrow SE( *(Rb + (Ri << sa2)) );

Syntax: I. ld.sh Rd, Rp++ II. ld.sh Rd, --Rp III. ld.sh Rd, Rp[disp] IV. ld.sh Rd, Rp[disp] V. ld.sh Rd, Rb[Ri<<sa]

Operands: I-V. d, p, b, i \in {0, 1, ..., 15} III. disp \in {0, 2, ..., 14} IV. disp \in {-32768, -32767, ..., 32767} V. sa \in {0, 1, 2, 3}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: 15 13 12 9 8 4 3 0 0 0 0 Rp 1 0 0 0 1 Rd

180 AVR32 32000D–04/2011

Format II: 15 13 12 9 8 4 3 0 0 0 0 Rp 1 0 1 0 1 Rd

Format III: 15 13 12 9 8 7 6 4 3 0 1 0 0 Rp 0 0 disp3 Rd

Format IV: 31 29 28 25 24 20 19 16 1 1 1 Rp 1 0 0 0 0 Rd 15 0 disp16

Format V: 31 29 28 25 24 20 19 16 1 1 1 Rb 0 0 0 0 0 Ri 15 12 11 8 7 6 5 4 3 0 0 0 0 0 0 1 0 0 0 0 Shift Amount Rd

Note: Format I and II: If Rd = Rp, the result is UNDEFINED.

32000D–04/2011 181

LD.SH{cond4} – Conditionally Load Sign-extended Halfword

Architecture revision 2 and higher.

Description Reads the halfword memory location specified and sign-extends it if the given condition is satisfied.

Operation: I. if (cond4) Rd ← SE( *(Rp + (ZE(disp9<<1))) );

Syntax: I. ld.sh{cond4} Rd, Rp[disp]

Operands: I. d, p ∈ {0, 1, ..., 15} disp ∈ {0, 2, ..., 1022} cond4 ∈ {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

182 AVR32 32000D–04/2011

LD.UH – Load Zero-extended Halfword

Description Reads the halfword memory location specified and zero-extends it.

Operation: I. Rd \leftarrow ZE( *(Rp) ); Rp \leftarrow Rp + 2; II. Rp \leftarrow Rp - 2; Rd \leftarrow ZE( *(Rp) ); III. Rd \leftarrow ZE( *(Rp + (ZE(displ3) << 1)) ); IV. Rd \leftarrow ZE( *(Rp + (SE(displ6))) ); V. Rd \leftarrow ZE( *(Rb + (Ri << sa2)) );

Syntax: I. ld.uh Rd, Rp++ II. ld.uh Rd, --Rp III. ld.uh Rd, Rp[disp] IV. ld.uh Rd, Rp[disp] V. ld.uh Rd, Rb[Ri<<sa]

Operands: I-V. d, p, b, i \in {0, 1, ..., 15} III. disp \in {0, 2, ..., 14} IV. disp \in {-32768, -32767, ..., 32767} V. sa \in {0, 1, 2, 3}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: 15 13 12 9 8 4 3 0 ┌───┬───┬───────────────┬───┬───┬───┬───┬───┬───────┐ │ 0 │ 0 │ 0 Rp │ 1 │ 0 │ 0 │ 1 │ 0 │ Rd │ └───┴───┴───────────────┴───┴───┴───┴───┴───┴───────┘

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AMEL

Format II: 15 13 12 9 8 4 3 0 0 0 0 Rp 1 0 1 1 0 Rd

Format III: 15 13 12 9 8 7 6 4 3 0 1 0 0 Rp 0 1 disp3 Rd

Format IV: 31 29 28 25 24 20 19 16 1 1 1 Rp 1 0 0 0 1 Rd 15 0 disp16

Format V: 31 29 28 25 24 20 19 16 1 1 1 Rb 0 0 0 0 0 Ri 15 12 11 8 7 6 5 4 3 0 0 0 0 0 0 1 0 1 0 0 Shift Amount Rd

Note: Format I and II: If Rd = Rp, the result is UNDEFINED.

184 AVR32 32000D-04/2011

LD.UH{cond4} – Conditionally Load Zero-extended Halfword

Architecture revision 2 and higher.

Description Reads the halfword memory location specified and zero-extends it if the given condition is satisfied.

Operation: I. if (cond4) Rd ← ZE( *(Rp + (ZE(dispp<<1)) ) );

Syntax: I. ld.uh{cond4} Rd, Rp[disp]

Operands: I. d, p ∈ {0, 1, ..., 15} disp ∈ {0, 2, ..., 1022} cond4 ∈ {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rp | 1 | 1 | 1 | 1 | 1 | Rd | 15 12 11 8 7 6 5 4 3 0 | cond4 | 0 | 1 | 0 | disp9 |

32000D–04/2011 185

LD.W – Load Word

Description

Format I to V: Reads the word memory location specified. Format VI: This instruction extracts a specified byte from Ri. This value is zero-extended, shifted left two positions and added to Rb to form an address. The contents of this address is loaded into Rd. The instruction is useful for indexing tables.

Operation:

I. Rd \leftarrow *(Rp); Rp \leftarrow Rp + 4; II. Rp \leftarrow Rp - 4; Rd \leftarrow *(Rp); III. Rd \leftarrow *(Rp + (ZE(disp5) \ll 2)); IV. Rd \leftarrow *(Rp + (SE(disp16)));) V. Rd \leftarrow *(Rb + (Ri \ll sa2)); VI. If (part == b) Rd \leftarrow *(Rb + (Ri[7:0] \ll 2) ); else if (part == l) Rd \leftarrow *(Rb + (Ri[15:8] \ll 2) ); else if (part == u) Rd \leftarrow *(Rb + (Ri[23:16] \ll 2) ); else Rd \leftarrow *(Rb + (Ri[31:24] \ll 2) );

Syntax:

I. ld.w Rd, Rp++ II. ld.w Rd, --Rp III. ld.w Rd, Rp[disp] IV. ld.w Rd, Rp[disp] V. ld.w Rd, Rb[Ri<<sa] VI. ld.w Rd, Rb[Ri: << 2]

Operands:

I-V. d, p, b, i \in \0, 1, ..., 15
III. disp \in \0, 4, ..., 124
IV. disp \in -32768, -32767, ..., 32767
V. sa \in \0, 1, 2, 3
VI. {d, b, i} \in \0, 1, ..., 15
part \in \t, u, l, b\

186 AVR32 32000D-04/2011

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

Format I: 15 13 12 9 8 4 3 0 ┌───┬───┬───────┬───┬───────────┬───────┐ │ 0 │ 0 │ 0 Rp│ 1 │ 0 0 0 0 │ 3...0 Rd│ └───┴───┴───────┴───┴───────────┴───────┘

Format II: 15 13 12 9 8 4 3 0 ┌──────┬───────┬───┬───────────┬───────┐ │ 0 │ 0 │ 0 Rp│ 1 │ 0 1 0 0 │ 3...0 Rd│ └───┴───┴───────┴───┴───────────┴───────┘

Format III: 15 13 12 9 8 4 3 0 ┌───┬───┬───────┬───┬───────────┬───────┐ │ 0 │ 1 │ 1 Rp│ │ disp5 │ 3...0 Rd│ └───┴───┴───────┴───┴───────────┴───────┘

Format IV: 31 29 28 25 24 20 19 16 ┌───┬───┬───────┬───┬───────────┬───────┐ │ 1 │ 1 │ 1 Rp│ 0 │ 1 1 1 1 │ 3...0 Rd│ └───┴───┴───────┴───┴───────────┴───────┘ 15 0 ┌─────────────────────────────────────────────┐ │ disp16 │ └─────────────────────────────────────────────┘

Format V: 31 29 28 25 24 20 19 16 ┌───┬───┬───────┬──────────────┬───────┐ │ 1 │ 1 │ 1 Rb│ 0 │ 0 0 0 0 │ 3...0 Ri│ └───┴───┴───────┴───┴───────────┴───────┘ 15 12 11 8 7 6 5 4 3 0 ┌───┬───┬───┬───┬───┬───┬──────────┬───────┐ │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ 1 1 0 0│Shift Amount│ 3...0 Rd│ └───┴───┴───┴───┴───┴───┴──────────┴───────┘

Format VI: 31 29 28 25 24 20 19 16 ┌──────┬───────┬───┬───────────┬───────┐ │ 1 │ 1 │ 1 Rb│ 0 │ 0 0 0 0 │ 3...0 Ri│ └──────┴───────┴───┴───────────┴───────┘ 15 12 11 6 5 4 3 0 ┌──────┬──────┬──────┬──────────┐ │ 0 │ 0 │ 0 │ 0 │ 1 │ 1 │ 1 │ 1 1 0│ X │ Y │ 3...0 Rd│ └───┴───┴───┴───┴───┴───┴───┴───────┘

Note: Format I and II: If Rd = Rp, the result is UNDEFINED.

32000D-04/2011 ATMEL® 187

188 AVR32 32000D–04/2011

LD.W{cond4} – Conditionally Load Word

Architecture revision 2 and higher.

Description Reads the word memory location specified if the given condition is satisfied.

Operation: I. if (cond4) Rd \leftarrow *(Rp + (ZE(disp9<<2)));

Syntax: I. ld.w{cond4} Rd, Rp[disp]

Operands: I. d, p \in {0, 1, ..., 15} disp \in {0, 4, ..., 2044} cond4 \in {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rp | 1 | 1 | 1 | 1 | 1 | Rd | 15 12 11 8 7 6 5 4 3 0 | cond4 | 0 | 0 | 0 | disp9 |

32000D-04/2011 ATMEL 189

LDC.{D,W} – Load Coprocessor

Description

Reads the memory location specified into the addressed coprocessor.

Operation:

I. CP#(CRd+1:CRd) \leftarrow *(Rp + (ZE(disp8) << 2)); II. Rp \leftarrow Rp-8; CP#(CRd+1:CRd) \leftarrow *(Rp); III. CP#(CRd+1:CRd) \leftarrow *(Rb + (Ri << sa2)); IV. CP#(CRd) \leftarrow *(Rp + (ZE(disp8) << 2)); V. Rp \leftarrow Rp-4; CP#(CRd) \leftarrow *(Rp); VI. CP#(CRd) \leftarrow *(Rb + (Ri << sa2));

Syntax:

I. ldc.d CP#, CRd, Rp[disp] II. ldc.d CP#, CRd, --Rp III. ldc.d CP#, CRd, Rb[Ri<<sa] IV. ldc.w CP#, CRd, Rp[disp] V. ldc.w CP#, CRd, --Rp VI. ldc.w CP#, CRd, Rb[Ri<<sa]

Operands:

I-VI. # \in {0, 1, ..., 7} I-II, IV-V.p \in {0, 1, ..., 15} I-III. d \in {0, 2, ..., 14} I, IV. disp \in {0, 4, ..., 1020} III, VI. {b, i} \in {0, 1, ..., 15} III, VI. sa \in {0, 1, 2, 3}

Status Flags:

Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

190 AVR32 32000D–04/2011

Format I: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | Rp | 15 13 12 11 8 7 0 | CP # | 1 | CRd[3:1] | 0 | disp8 |

Format II: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | Rp | 15 13 12 11 9 8 7 0 | CP # | 0 | CRd[3:1] | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |

Format III: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | Rp | 15 13 12 11 9 8 7 6 5 4 3 0 | CP # | 1 | CRd[3:1] | 0 | 0 | 1 | Sh amt | Ri |

Format IV: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | Rp | 15 13 12 11 8 7 0 | CP # | 0 | CRd | k8 |

Format V: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | Rp | 15 13 12 11 8 7 0 | CP # | 0 | CRd | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |

Format VI: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | Rp | 15 13 12 11 8 7 6 5 4 3 0 | CP # | 1 | CRd | 0 | 0 | Sh amt | Ri |

Example: ldc.d CP2, CR0, R2[0]

32000D–04/2011 ATMEL® 191

LDC0.{D,W} – Load Coprocessor 0

Description Reads the memory location specified into coprocessor 0.

Operation: I. CP0(CRd+1:CRd) \leftarrow *(Rp + (ZE(displ2) << 2)); II. CP0(CRd) \leftarrow *(Rp + (ZE(displ2) << 2));

Syntax: I. ldc0.d CRd, Rp[disp] II. ldc0.w CRd, Rp[disp]

Operands: I,II p \in {0, 1, ..., 15} I. d \in {0, 2, ..., 14} II. d \in {0, 1, ..., 15} I, II. disp \in {0, 4, ..., 16380}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 31 & & 29 & 28 & & & & 25 & 24 & & & & & & & 20 & 19 & & & & & & & & & & & & 16 \ \hline 1 & 1 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & \multicolumn{6}{c|}{Rp} \ \hline 15 & & 13 & 12 & 11 & & & 8 & 7 & & & & & & & & & & & & & & & & & & & & 0 \ \hline \multicolumn{4}{|c|}{disp[11:8]} & \multicolumn{4}{|c|}{CRd[3:1]} & 0 & \multicolumn{8}{c|}{disp[7:0]} \ \hline \end{tabular}

Format II:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 31 & & 29 & 28 & & & & 25 & 24 & & & & & & & 20 & 19 & & & & & & & & & & & & 16 \ \hline 1 & 1 & 1 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & \multicolumn{6}{c|}{Rp} \ \hline 15 & & 12 & 11 & & & & 8 & 7 & & & & & & & & & & & & & & & & & & & & 0 \ \hline \multicolumn{4}{|c|}{disp[11:8]} & \multicolumn{8}{|c|}{CRd} & \multicolumn{8}{c|}{disp[7:0]} \ \hline \end{tabular}

Example: ldc0.d CR0, R2[0]

192 AVR32 32000D-04/2011

LDCM.{D,W} – Load Coprocessor Multiple Registers

Architecture revision:

Description

Reads the memory locations specified into the addressed coprocessor. The pointer register can optionally be updated after the operation.

Operation:

I.
Loadaddress ← Rp;
for (i = 7 to 0)
if ReglistCPD8[i] == 1 then
CP#(CR(2*i+1)) ← (Loadaddress++);
CP#(CR(2i)) ← *(Loadaddress++);
if Opcode[++] == 1 then
Rp ← Loadaddress;

II.
Loadaddress ← Rp;
for (i = 7 to 0)
if ReglistCPH8[i] == 1 then
CP#(CRi+8) ← *(Loadaddress++);
if Opcode[++] == 1 then
Rp ← Loadaddress;

III.
Loadaddress ← Rp;
for (i = 7 to 0)
if ReglistCPL8[i] == 1 then
CP#(CRi) ← *(Loadaddress++);
if Opcode[++] == 1 then
Rp ← Loadaddress;

Syntax:

I. ldcM.d CP#, Rp{++}, ReglistCPD8
II. ldcM.w CP#, Rp{++}, ReglistCPH8
III. ldcM.w CP#, Rp{++}, ReglistCPL8

Operands:

I-III. # ∈ {0, 1, ..., 7}
p ∈ {0, 1, ..., 15}

I. ReglistCPD8 ∈ {CR0-CR1,CR2-CR3,CR4-CR5,CR6-CR7,CR8-CR9,
CR10-CR11,CR12-CR13,CR14-CR15}

II. ReglistCPH8 ∈ {CR8, CR9, CR10, ..., CR15}

III. ReglistCPL8 ∈ {CR0, CR1, CR2, ..., CR7}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

Format I: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | Rp | 15 13 12 11 8 7 0 | CP# | ++ | 0 | 1 | 0 | 0 | CR 15-14 | CR 13-12 | CR 11-10 | CR 9-8 | CR 7-6 | CR 5-4 | CR 3-2 | CR 1-0 |

Format II: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | Rp | 15 13 12 11 8 7 0 | CP# | ++ | 0 | 0 | 0 | 1 | CR 15 | CR 14 | CR 13 | CR 12 | CR 11 | CR 10 | CR 9 | CR 8 |

Format III: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | Rp | 15 13 12 11 8 7 0 | CP# | ++ | 0 | 0 | 0 | 0 | CR 7 | CR 6 | CR 5 | CR 4 | CR 3 | CR 2 | CR 1 | CR 0 |

Example: Idcm.w CP2, SP++, CR2-CR5

Note: Emtpy ReglistCPL8/ReglistCPL8/ReglistCPD8 gives UNDEFINED result.

LDDPC – Load PC-relative with Displacement

Description Performs a PC relative load of a register

Operation: I. Rd ← *( (PC & 0xFFFF_FFFC) + (ZE(disp7) << 2));

Syntax: I. lddpc Rd, PC[disp]

Operands: I. d ∈ {0, 1, ..., 15} disp ∈ {0, 4, ..., 508}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: 15 13 12 11 10 4 3 0 ┌───┬───┬───┬───┬───────────────┬───┬───┐ │ 0 │ 1 │ 0 │ 0 │ 1 │ disp7 │ 0 │ Rd │ └───┴───┴───┴───┴───────────────┴──────┘

32000D–04/2011 ATMEL® 195