Atmel AVR32 user guide: Format II

Format II:

270 AVR32 32000D–04/2011

PAVG.{UB/SH} – Packed Average

Description Computes the average of pairs of packed unsigned bytes (pavg.ub) or packed signed halfwords (pavg.sh). The averages are computed by adding two values together while also adding in a rounding factor in the least significant bit. The result is then halved by shifting it one position to the right.

Operation: I. Rd[31:24] \leftarrow LSR(ZE(Rx[31:24], 9) + ZE(Ry[31:24], 9) + 1, 1); Rd[23:16] \leftarrow LSR(ZE(Rx[23:16], 9) + ZE(Ry[23:16], 9) + 1, 1); Rd[15:8] \leftarrow LSR(ZE(Rx[15:8], 9) + ZE(Ry[15:8], 9) + 1, 1); Rd[7:0] \leftarrow LSR(ZE(Rx[7:0], 9) + ZE(Ry[7:0], 9) + 1, 1); II. Rd[31:16] \leftarrow ASR(SE(Rx[31:16], 17) + SE(Ry[31:16], 17) + 1, 1); Rd[15:0] \leftarrow ASR(SE(Rx[15:0], 17) + SE(Ry[15:0], 17) + 1, 1);

Syntax: I. pavg.ub Rd, Rx, Ry II. pavg.sh Rd, Rx, Ry

Operands: I, II. {d, x, y} \in {0, 1, ..., 15}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 4 3 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | Rd |

32000D-04/2011 ATMEL® 271

Format II:

272 AVR32 32000D–04/2011

PLSL.{B/H} – Packed Logical Shift Left

Description Perform a logical shift left on each of the packed bytes or halfwords in the source register and store the result to the destination register.

Operation: I. Rd[31:24] ← LSL(Rs[31:24], sa3); Rd[23:16] ← LSL(Rs[23:16], sa3); Rd[15:8] ← LSL(Rs[15:8], sa3); Rd[7:0] ← LSL(Rs[7:0], sa3); II. Rd[31:16] ← LSL(Rs[31:16], sa4); Rd[15:0] ← LSL(Rs[15:0], sa4);

Syntax: I. plsl.b Rd, Rs, sa II. plsl.h Rd, Rs, sa

Operands: I, II. {d, s} ∈ {0, 1, ..., 15} I. sa ∈ {0, 1, ..., 7} II. sa ∈ {0, 1, ..., 15}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: 31 29 28 25 24 19 18 16 | 1 | 1 | 1 | Rs | 0 | 0 | 0 | 0 | 0 | 0 | sa3 | 15 4 3 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | Rd |

ATMEL® 32000D–04/2011 273

Format II:

PLSR.{B/H} – Packed Logical Shift Right

Description Perform a logical shift right on each of the packed bytes or halfwords in the source register and store the result to the destination register.

Operation: I. Rd[31:24] \leftarrow LSR(Rs[31:24], sa3); Rd[23:16] \leftarrow LSR(Rs[23:16], sa3); Rd[15:8] \leftarrow LSR(Rs[15:8], sa3); Rd[7:0] \leftarrow LSR(Rs[7:0], sa3); II. Rd[31:16] \leftarrow LSR(Rs[31:16], sa4); Rd[15:0] \leftarrow LSR(Rs[15:0], sa4);

Syntax: I. plsr.b Rd, Rs, sa II. plsr.h Rd, Rs, sa

Operands: I, II. {d, s} \in {0, 1, ..., 15} I. sa \in {0, 1, ..., 7} II. sa \in {0, 1, ..., 15}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: 31 29 28 25 24 19 18 16 | 1 | 1 | 1 | Rs | 0 | 0 | 0 | 0 | 0 | 0 | sa3 | 15 4 3 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | Rd |

32000D–04/2011 ATMEL® 275

Format II:

276 AVR32 32000D–04/2011

PMAX.{UB/SH} – Packed Maximum Value

Description

Compute the maximum values of pairs of packed unsigned bytes (pmax.ub) or packed signed halfwords (pmax.sh).

Operation: I. If ( Rx[31:24] > Ry[31:24] ) then Rd[31:24] \leftarrow Rx[31:24] else Rd[31:24] \leftarrow Ry[31:24] ; If ( Rx[23:16] > Ry[23:16] ) then Rd[23:16] \leftarrow Rx[23:16] else Rd[23:16] \leftarrow Ry[23:16] ; If ( Rx[15:8] > Ry[15:8] ) then Rd[15:8] \leftarrow Rx[15:8] else Rd[15:8] \leftarrow Ry[15:8] ; If ( Rx[7:0] > Ry[7:0] ) then Rd[7:0] \leftarrow Rx[7:0] else Rd[7:0] \leftarrow Ry[7:0] ; II. If ( Rx[31:16] > Ry[31:16] ) then Rd[31:16] \leftarrow Rx[31:16] else Rd[31:16] \leftarrow Ry[31:16] ; If ( Rx[15:0] > Ry[15:0] ) then Rd[15:0] \leftarrow Rx[15:0] else Rd[15:0] \leftarrow Ry[15:0] ;

Syntax: I. pmax.ub Rd, Rx, Ry II. pmax.sh Rd, Rx, Ry

Operands: I, II. {d, x, y} \in {0, 1, ..., 15}

Status Flags: Format I: Q: Not affected. V: ( Rx[7:0] > Ry[7:0] ) N: ( Rx[15:8] > Ry[15:8] ) Z: ( Rx[23:16] > Ry[23:16] ) C: ( Rx[31:24] > Ry[31:24] )

Format II: Q: Not affected. V: Not affected. N: Not affected. Z: ( Rx[15:0] > Ry[15:0] ) C: ( Rx[31:16] > Ry[31:16] )

Opcode: Format I: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 4 3 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | Rd |

ATMEL 32000D–04/2011 277

Format II:

278 AVR32 32000D–04/2011

PMIN.{UB/SH} – Packed Minimum Value

Description

Compute the minimum values of pairs of packed unsigned bytes (pmin.ub) or packed signed halfwords (pmin.sh).

Operation: I. If ( Rx[31:24] < Ry[31:24] ) then Rd[31:24] ← Rx[31:24] else Rd[31:24] ← Ry[31:24] ; If ( Rx[23:16] < Ry[23:16] ) then Rd[23:16] ← Rx[23:16] else Rd[23:16] ← Ry[23:16] ; If ( Rx[15:8] < Ry[15:8] ) then Rd[15:8] ← Rx[15:8] else Rd[15:8] ← Ry[15:8] ; If ( Rx[7:0] < Ry[7:0] ) then Rd[7:0] ← Rx[7:0] else Rd[7:0] ← Ry[7:0] ; II. If ( Rx[31:16] < Ry[31:16] ) then Rd[31:16] ← Rx[31:16] else Rd[31:16] ← Ry[31:16] ; If ( Rx[15:0] < Ry[15:0] ) then Rd[15:0] ← Rx[15:0] else Rd[15:0] ← Ry[15:0] ;

Syntax: I. pmin.ub Rd, Rx, Ry II. pmin.sh Rd, Rx, Ry

Operands: I, II. {d, x, y} ∈ {0, 1, ..., 15}

Status Flags: Format I: Q: Not affected. V: ( Rx[7:0] < Ry[7:0] ) N: ( Rx[15:8] < Ry[15:8] ) Z: ( Rx[23:16] < Ry[23:16] ) C: ( Rx[31:24] < Ry[31:24] )

Format II: Q: Not affected. V: Not affected. N: Not affected. Z: ( Rx[15:0] < Ry[15:0] ) C: ( Rx[31:16] < Ry[31:16] )

Opcode: Format I: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 4 3 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | Rd |

32000D-04/2011 ATMEL® 279

Format II:

AVR32

POPJC – Pop Java Context from Frame

Description Fetch the system registers LV0 to LV7 used in Java state from the current method frame. The register FRAME (equal to R9) is used as pointer register.

Operation: I. temp \leftarrowFRAME; JAVA_LV0 \leftarrow*(temp--); JAVA_LV1 \leftarrow*(temp--); JAVA_LV2 \leftarrow*(temp--); JAVA_LV3 \leftarrow*(temp--); JAVA_LV4 \leftarrow*(temp--); JAVA_LV5 \leftarrow*(temp--); JAVA_LV6 \leftarrow*(temp--); JAVA_LV7 \leftarrow*(temp--);

Syntax: I. popjc

Operands: I. none

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: \begin{tabular}{|c|c|c|c|c|c|c|c||c|c|c|c|c|c||c|c|c|c|} \hline 1 & 1 & 0 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 1 \ \hline \end{tabular} 15 \hspace{8em} 9 \quad 8 \hspace{5em} 4 \quad 3 \hspace{4em} 0

32000D–04/2011 \hspace{10em} ATMEL \hspace{10em} 281

POPM – Pop Multiple Registers from Stack

Description

Loads the consecutive words pointed to by SP into the registers specified in the instruction. The PC can be loaded, resulting in a jump to the loaded value. If PC is popped, the return value in R12 is tested and the flags are updated. R12 can optionally be updated with -1, 0 or 1. The k bit in the instruction coding is used to optionally let the POPM instruction update the return register R12 with the values -1, 0 or 1.

Operation:

I. if Reglist8[PC] \wedge k == B'1 PC \leftarrow *(SP++) if Reglist8[LR:R12] == B'00 R12 \leftarrow 0; else if Reglist8[LR:R12] == B'01 R12 \leftarrow 1; else R12 \leftarrow -1; Test R12 and update flags; else if Reglist8[PC] == 1 then PC \leftarrow *(SP++); if Reglist8[LR] == 1 then LR \leftarrow *(SP++); if Reglist8[R12] == 1 then R12 \leftarrow *(SP++); if Reglist8[PC] == 1 then Test R12 and update flags;

if Reglist8[5] == 1 then R11 \leftarrow *(SP++); if Reglist8[4] == 1 then R10 \leftarrow *(SP++); if Reglist8[3] == 1 then R9 \leftarrow *(SP++); R8 \leftarrow *(SP++); if Reglist8[2] == 1 then R7 \leftarrow *(SP++); R6 \leftarrow *(SP++); R5 \leftarrow *(SP++); R4 \leftarrow *(SP++); if Reglist8[1] == 1 then R3 \leftarrow *(SP++);

282 AVR32 32000D-04/2011

R2 \leftarrow *(SP++); R1 \leftarrow *(SP++); R0 \leftarrow *(SP++);

Syntax: I. popm Reglist8 {, R12 = {-1, 0, 1}} If the optional R12 = {-1, 0, 1} parameter is specified, PC must be in Reglist8. If the optional R12 = {-1, 0, 1} parameter is specified, LR should NOT be in Reglist8.

Operands: I. Reglist8 \in {R0- R3, R4-R7, R8-R9, R10,R11, R12, LR, PC}

Status Flags: Flags are only updated if Reglist8[PC] == 1. They are set as the result of the operation cp R12, 0

Q: Not affected V: V \leftarrow 0 N: N \leftarrow RES[31] Z: Z \leftarrow (RES[31:0] == 0) C: C \leftarrow 0

Opcode:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & & & & & & & & & & & & 3 & 2 & & 0 \ \hline 1 & 1 & 0 & 1 & PC & LR & 12 & 11 & 10 & 9-8 & 7-4 & 3-0 & k & 0 & 1 & 0 \ \hline \end{tabular}

Note: Emtpy Reglist8 gives UNDEFINED result. The R bit in the status register has no effect on this instruction.

32000D-04/2011 ATMEL 283

PREF – Cache Prefetch

Description

This instruction allows the programmer to explicitly state that the cache should prefetch the specified line. The memory system treats this instruction in an implementation-dependent manner, and implementations without cache treats the instruction as a NOP. A prefetch instruction never reduces the performance of the system. If the prefetch instruction performs an action that would lower the system performance, it is treated as a NOP. For example, if the prefetch instruction is about to generate an addressing exception, the instruction is cancelled and no exception is taken.

Operation:

I. Prefetch cache line containing the address (Rp + SE(displ6)).

Syntax:

pref Rp[disp]

Operands:

I. p \in \0, 1, ..., 15
disp \in -32768, -32767, ..., 32767\

Status Flags:

Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

284 AVR32 32000D–04/2011

PSAD – Packed Sum of Absolute Differences

Architecture revision:

Description

Compute the Sum of Absolute Differences (SAD) of four pairs of packed unsigned bytes from the source registers and store the result in the destination register.

Operation:

I. Rd ← | Rx[31:24] - Ry[31:24] | + | Rx[23:16] - Ry[23:16] | + | Rx[15:8] - Ry[15:8] | + | Rx[7:0] - Ry[7:0] |;

Syntax:

I. psad Rd, Rx, Ry

Operands:

I, II. {d, x, y} ∈ {0, 1, ..., 15}

Status Flags:

• Q: Not affected.
• V: Not affected.
• N: Not affected.
• Z: Not affected.
• C: Not affected.

Opcode:

Format I:

PSUB.{B/H} – Packed Subtraction

Description

Perform subtraction of four pairs of packed bytes (psub.b) or two pairs of halfwords (psub.h). Upon overflow any additional bits are discarded and the result is wrapped around.

Operation:

I. Rd[31:24] \leftarrow Rx[31:24] - Ry[31:24]; Rd[23:16] \leftarrow Rx[23:16] - Ry[23:16]; Rd[15:8] \leftarrow Rx[15:8] - Ry[15:8]; Rd[7:0] \leftarrow Rx[7:0] - Ry[7:0]; II. Rd[31:16] \leftarrow Rx[31:16] - Ry[31:16]; Rd[15:0] \leftarrow Rx[15:0] - Ry[15:0];

Syntax:

I. psub.b Rd, Rx, Ry II. psub.h Rd, Rx, Ry

Operands:

I, II. {d, x, y} \in {0, 1, ..., 15}

Status Flags:

Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

Format I: Format II:

286 AVR32 32000D-04/2011

PSUBADD.H – Packed Halfword Subtraction and Addition

Description Perform an subtraction and addition on the same halfword operands which are selected from the source registers. The two halfword results are packed into the destination register without performing any saturation.

Operation:

I. If (Rx-part == t) then operand1 = Rx[31:16] else operand1 = Rx[15:0]; If (Ry-part == t) then operand2 = Ry[31:16] else operand2 = Ry[15:0]; Rd[31:16] \leftarrow operand1 - operand2; Rd[15:0] \leftarrow operand1 + operand2;

Syntax: I. psubadd.h Rd, Rx:, Ry:

Operands: I. {d, x, y} \in {0, 1, ..., 15} part \in {t,b}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 0 0 0 0 | Ry | 15 6 5 4 3 0 | 0 | 0 | 1 | 0 0 0 0 | 1 0 1 | X | Y | Rd |

32000D–04/2011 ATMEL® 287

ATMEL

PSUBADDH.SH – Packed Signed Halfword Subtraction and Addition with Halving

Description

Perform a subtraction and addition on the same halfword operands which are selected from the source registers. The halfword results are halved in order to prevent any overflows from occuring

Operation:

I. If (Rx-part == t) then operand1 = Rx[31:16] else operand1 = Rx[15:0]; If (Ry-part == t) then operand2 = Ry[31:16] else operand2 = Ry[15:0]; Rd[31:16] \leftarrow ASR(SE(operand1, 17) - SE(operand2, 17), 1); Rd[15:0] \leftarrow ASR(SE(operand1, 17) + SE(operand2, 17), 1);

Syntax:

I. psubaddh.sh Rd, Rx:, Ry:

Operands:

I. {d, x, y} \in {0, 1, ..., 15} part \in {t,b}

Status Flags:

Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

Format I:

• \begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c ........ } \hline
• 31 & & 29 & 28 & & & & & 25 & 24 & & & & & & & & & & & 20 & 19 & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & ........ \ \hline 1 & 1 & 1 & \multicolumn{4}{c|}{Rx} & \multicolumn{5}{c|}{0 0 0 0 0} & \multicolumn{6}{c|}{Ry} \ \hline
• 15 & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & ........

PSUBADDS.{UH/SH} – Packed Halfword Subtraction and Addition with Saturation

Architecture revision:

Description

Perform a subtraction and addition on the same halfword operands which are selected from the source registers. The resulting halfwords are saturated to unsigned halfwords (psubadds.uh) or signed halfwords (psubadds.sh) and then packed together in the destination register.

Operation:

I. If (Rx-part == t) then operand1 = Rx[31:16] else operand1 = Rx[15:0]; If (Ry-part == t) then operand2 = Ry[31:16] else operand2 = Ry[15:0]; Rd[31:16] ← SATSU(ZE(operand1, 17) - ZE(operand2, 17), 16); Rd[15:0] ← SATU(ZE(operand1, 17) + ZE(operand2, 17), 16); II. If (Rx-part == t) then operand1 = Rx[31:16] else operand1 = Rx[15:0]; If (Ry-part == t) then operand2 = Ry[31:16] else operand2 = Ry[15:0]; Rd[31:16] ← SATS(SE(operand1, 17) - SE(operand2, 17), 16 ); Rd[15:0] ← SATS(SE(operand1, 17) + SE(operand2, 17), 16);

Syntax:

I. psubadds.uh Rd, Rx:<part>, Ry:<part> II. psubadds.sh Rd, Rx:<part>, Ry:<part>

Operands:

I. {d, x, y} ∈ {0, 1, ..., 15} part ∈ {t,b}

Status Flags:

Q: Flag set if saturation occured in one or more of the partial operations. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

Format I:

ATMEL

Format II:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline

• \multicolumn{3}{|c|}{31 \quad 29} & \multicolumn{4}{|c|}{28 \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \ ........ \quad 25} & \multicolumn{5}{|c|}{24 \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \ ........ \quad 20} & \multicolumn{4}{|c|}{19 \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \ ........

PSUBH.{UB/SH} – Packed Subtraction with Halving

Description Perform subtraction of four pairs of packed unsigned bytes (psub.ub) or two pairs of signed half-words (psub.sh) with a halflng of the result to prevent any overflows from occuring.

Operation: I. Rd[31:24] \leftarrow LSR(ZE(Rx[31:24], 9) - ZE(Ry[31:24], 9), 1); Rd[23:16] \leftarrow LSR(ZE(Rx[23:16], 9) - ZE(Ry[23:16], 9), 1); Rd[15:8] \leftarrow LSR(ZE(Rx[15:8], 9) - ZE(Ry[15:8], 9), 1); Rd[7:0] \leftarrow LSR(ZE(Rx[7:0], 9) - ZE(Ry[7:0], 9), 1); II. Rd[31:16] \leftarrow ASR(SE(Rx[31:16], 17) - SE(Ry[31:16], 17), 1); Rd[15:0] \leftarrow ASR(SE(Rx[15:0], 17) - SE(Ry[15:0], 17), 1);

Syntax: I. psubh.ub Rd, Rx, Ry II. psubh.sh Rd, Rx, Ry

Operands: I, II. {d, x, y} \in {0, 1, ..., 15}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: Format II:

32000D–04/2011 ATMEL® 291

PSUBS.{UB/SB/UH/SH} – Packed Subtraction with Saturation

Description

Perform subtraction of four pairs of packed bytes or two pairs of halfwords. The result is saturated to either unsigned bytes (psubs.ub), signed bytes (psubs.sb), unsigned halfwords (psubs.uh) or signed halfwords (psubs.sh).

Operation:

I. Rd[31:24] \leftarrow SATSU(ZE(Rx[31:24], 9) - ZE(Ry[31:24], 9), 8); Rd[23:16] \leftarrow SATSU(ZE(Rx[23:16], 9) - ZE(Ry[23:16], 9), 8); Rd[15:8] \leftarrow SATSU(ZE(Rx[15:8], 9) - ZE(Ry[15:8], 9), 8); Rd[7:0] \leftarrow SATSU(ZE(Rx[7:0], 9) - ZE(Ry[7:0], 9), 8);

II. Rd[31:24] \leftarrow SATS(SE(Rx[31:24], 9) - SE(Ry[31:24], 9), 8); Rd[23:16] \leftarrow SATS(SE(Rx[23:16], 9) - SE(Ry[23:16], 9), 8); Rd[15:8] \leftarrow SATS(SE(Rx[15:8], 9) - SE(Ry[15:8], 9), 8); Rd[7:0] \leftarrow SATS(SE(Rx[7:0], 9) - SE(Ry[7:0], 9), 8);

III. Rd[31:16] \leftarrow SATSU(ZE(Rx[31:16], 17) - ZE(Ry[31:16], 17), 16); Rd[15:0] \leftarrow SATSU(ZE(Rx[15:0], 17) - ZE(Ry[15:0], 17), 16);

IV. Rd[31:16] \leftarrow SATS(SE(Rx[31:16], 17) - SE(Ry[31:16], 17), 16); Rd[15:0] \leftarrow SATS(SE(Rx[15:0], 17) - SE(Ry[15:0], 17), 16);

Syntax:

I. psubs.ub Rd, Rx, Ry II. psubs.sb Rd, Rx, Ry III. psubs.uh Rd, Rx, Ry IV. psubs.sh Rd, Rx, Ry

Operands:

I, II, III, IV.{d, x, y} \in {0, 1, ..., 15}

Status Flags:

Q: Flag set if saturation occured in one or more of the partial operations. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

Format I:

292 AVR32 32000D-04/2011

Format II: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 4 3 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | Rd |

Format III: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 4 3 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | Rd |

Format IV: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 4 3 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | Rd |

32000D–04/2011 ATMEL 293