Atmel AVR32 user guide: PSUBX.H – Packed Halfword Subtraction with Crossed Operand

PSUBX.H – Packed Halfword Subtraction with Crossed Operand

Description

Subtract the bottom halfword of Ry from the top halfword of Rx and the top halfword of Ry from the bottom halfword of Rx. The resulting halfwords are packed together in the destination register without performing any saturation.

Operation:

I. Rd[31:16] \leftarrow Rx[31:16] - Ry[15:0] ; Rd[15:0] \leftarrow Rx[15:0] - Ry[31:16];

Syntax:

I. psubx.h Rd, Rx, Ry

Operands:

I. {d, x, y} \in {0, 1, ..., 15}

Status Flags:

Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

Format I: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 4 3 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | Rd |

294 AVR32 32000D–04/2011

PSUBXH.SH – Packed Signed Halfword Subtraction with Crossed Operand and Halving

Description Subtract the bottom halfword of Ry from the top halfword of Rx and the top halfword of Ry from the bottom halfword of Rx. The resulting halfwords are halved in order to avoid any overflow and then packed together in the destination register.

Operation: I. Rd[31:16] \leftarrow ASR(SE(Rx[31:16], 17) - SE(Ry[15:0], 17), 1); Rd[15:0] \leftarrow ASR(SE(Rx[15:0], 17) - SE(Ry[31:16], 17), 1);

Syntax: I. psubxh.sh Rd, Rx, Ry

Operands: I. {d, x, y} \in {0, 1, ..., 15}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 4 3 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | Rd |

32000D–04/2011 ATMEL 295

PSUBXS.{UH/SH} – Packed Halfword Subtraction with Crossed Operand and Saturation

Description

Subtract the bottom halfword of Ry from the top halfword of Rx and the top halfword of Ry from the bottom halfword of Rx. The resulting halfwords are saturated to unsigned halfwords (psubxh.uh) or signed halfwords (psubxh.sh) and then packed together in the destination register.

Operation:

I. Rd[31:16] \leftarrow SATSU(ZE(Rx[31:16], 17) - ZE(Ry[15:0], 17), 16); Rd[15:0] \leftarrow SATSU(ZE(Rx[15:0], 17) - ZE(Ry[31:16], 17), 16); II. Rd[31:16] \leftarrow SATS(SE(Rx[31:16], 17) - SE(Ry[15:0], 17), 16); Rd[15:0] \leftarrow SATS(SE(Rx[15:0], 17) - SE(Ry[31:16], 17), 16);

Syntax:

I. psubxs.uh Rd, Rx, Ry II. psubxs.sh Rd, Rx, Ry

Operands:

I, II. {d, x, y} \in {0, 1, ..., 15}

Status Flags:

Q: Flag set if saturation occured in one or more of the partial operations. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

Format I: Format II:

296 AVR32 32000D-04/2011

32000D–04/2011 ATMEL® 297

PUNPCK{SB/UB}.H – Unpack bytes to halfwords

Description Unpack two unsigned bytes (punpckub.h) or two signed bytes (punpcksb.h) from the source register to two packed halfwords in the destination register.

Operation: I. If ( Rs-part == top ) then Rd[31:16] \leftarrow ZE(Rs[31:24], 16); Rd[15:0] \leftarrow ZE(Rs[23:16], 16); else Rd[31:16] \leftarrow ZE(Rs[15:8], 16); Rd[15:0] \leftarrow ZE(Rs[7:0], 16); II. If ( Rs-part == top ) then Rd[31:16] \leftarrow SE(Rs[31:24], 16); Rd[15:0] \leftarrow SE(Rs[23:16], 16); else Rd[31:16] \leftarrow SE(Rs[15:8], 16); Rd[15:0] \leftarrow SE(Rs[7:0], 16);

Syntax: I. punpckub.h Rd, Rs: II. punpcksb.h Rd, Rs:

Operands: I, II. {d, s} \in {0, 1, ..., 15} part \in {t, b}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: \begin{tabular}{|c|c|c|c c c c c c c c c c c c c|} \hline \multicolumn{4}{|c}{31 \quad 29 \quad 28} & \multicolumn{6}{c}{25} & \multicolumn{6}{c}{24 \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad \quad 16} \ \hline 1 & 1 & 1 & \multicolumn{6}{c|}{Rs} & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \ \hline \multicolumn{4}{|c}{15} & \multicolumn{6}{c}{5} & 4 & \multicolumn{2}{c|}{3} & \multicolumn{4}{c|}{0} \ \hline 0 & 0 & 1 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 0 & k & \multicolumn{2}{c|}{} & \multicolumn{4}{c|}{Rd} \ \hline \end{tabular}

298 AVR32 32000D-04/2011

Format II:

31 29 28 25 24 16 ┌───┬───┬───────────────┬───────────────────────────────────┐ │ 1 │ 1 │ 1 │ Rs │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ └───┴───┴───────────────┴───────────────────────────────────┘ 15 5 4 3 0 ┌──────┬──────┬──────┬──────┬──────┬──────┬──────┬──────┐ │ 0 │ 0 │ 1 │ 0 │ 0 │ 1 │ 0 │ 0 │ 1 │ 0 │ 1 │ k │ │ │ Rd │ └───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┘

32000D-04/2011 ATMEL® 299

ATMEL

PUSHJC – Push Java Context to Frame

Description Stores the system registers LV0 to LV7 used in Java state to designated place on the current method frame. FRAME (equal to R9) is used as pointer register.

Operation: I. temp \leftarrowFRAME; *(temp--) \leftarrowJAVA_LV0; *(temp--) \leftarrowJAVA_LV1; *(temp--) \leftarrowJAVA_LV2; *(temp--) \leftarrowJAVA_LV3; *(temp--) \leftarrowJAVA_LV4; *(temp--) \leftarrowJAVA_LV5; *(temp--) \leftarrowJAVA_LV6; *(temp--) \leftarrowJAVA_LV7;

Syntax: I. pushjc

Operands: I. none

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & \multicolumn{7}{c|}{9} & 8 & \multicolumn{5}{c|}{4} & 3 & \multicolumn{2}{c}{0} \ \hline 1 & 1 & 0 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 1 \ \hline \end{tabular}

300 AVR32 32000D–04/2011

AVR32

PUSHM – Push Multiple Registers to Stack

Description Stores the registers specified in the instruction into consecutive words pointed to by SP.

Operation:

1. if Reglist8[0] == 1 then *(--SP) \leftarrowR0; *(--SP) \leftarrowR1; *(--SP) \leftarrowR2; *(--SP) \leftarrowR3; if Reglist8[1] == 1 then *(--SP) \leftarrowR4; *(--SP) \leftarrowR5; *(--SP) \leftarrowR6; *(--SP) \leftarrowR7; if Reglist8[2] == 1 then *(--SP) \leftarrowR8; *(--SP) \leftarrowR9; if Reglist8[3] == 1 then *(--SP) \leftarrowR10; if Reglist8[4] == 1 then *(--SP) \leftarrowR11; if Reglist8[5] == 1 then *(--SP) \leftarrowR12; if Reglist8[6] == 1 then *(--SP) \leftarrowLR; if Reglist8[7] == 1 then *(--SP) \leftarrowPC;

Syntax:

1. pushm Reglist8

Operands:

1. Reglist8 \in {R0- R3, R4-R7, R8-R9, R10,R11, R12, LR, PC}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

32000D–04/2011 ATMEL 301

ATMEL®

Opcode: 15 13 12 11 4 3 0 | 1 | 1 | 0 | 1 | PC | LR | 12 | 11 | 10 | 9-8 | 7-4 | 3-0 | 0 | 0 | 0 | 1 |

Note: Emtpy Reglist8 gives UNDEFINED result. The R bit in the status register has no effect on this instruction.

302 AVR32 32000D–04/2011

AVR32

RCALL – Relative Subroutine Call

Description PC-relative call of subroutine

Operation: I. LR \leftarrow PC + 2 PC \leftarrow PC + (SE(disp10)<<1) II. LR \leftarrow PC + 4 PC \leftarrow PC + (SE(disp21)<<1)

Syntax: I. rcall PC[disp] II. rcall PC[disp]

Operands: I. disp \in {-1024, -1022, ..., 1022} II. disp \in {-2097152, -2097150, ..., 2097150}

Status Flags Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: Format II:

32000D-04/2011 303

RET{cond4} – Conditional Return from Subroutine

Architecture revision:

Description

Return from subroutine if the specified condition is true. Values are moved into the return register, the return value is tested, and flags are set.

Operation:

I. If (cond4) If (Rs != {LR, SP, PC}) R12 ← Rs; else if (Rs == LR) R12 ← -1; else if (Rs == SP) R12 ← 0; else R12 ← 1; Test R12 and set flags; PC ← LR;

Syntax:

I. ret{cond4} Rs

Operands:

I. cond4 ∈ {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} s ∈ {0, 1, ..., 15}

Status Flags:

Flags are set as result of the operation CP R12, 0. Q: Not affected V: V ← 0 N: N ← RES[31] Z: Z ← (RES[31:0] == 0) C: C ← 0

Opcode:

RETD – Return from Debug mode

Description Return from debug mode.

Operation: I. SR \leftarrow RSR_DBG PC \leftarrow RAR_DBG

Syntax: I. retd

Operands: None

Status Flags: Q: Not affected V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode:

Note: This instruction can only be executed in a privileged mode. Execution from any other mode will trigger a Privilege Violation exception.

32000D–04/2011 305

RETE – Return from event handler

Description

Returns from an exception or interrupt. SREG[L] is cleared to support atomic memory access with the stcond instruction. This instruction can only be executed in INT0-INT3, EX and NMI modes. Execution in Application or Supervisor modes will trigger a Privilege Violation exception.

Operation:

I. If (microarchitecture == AVR32A)

SR ← *(SP_SYS++) PC ← *(SP_SYS++) If ( SR[M2:M0] == {B'010, B'011, B'100, B'101} ) LR ← *(SP_SYS++) R12 ← *(SP_SYS++) R11 ← *(SP_SYS++) R10 ← *(SP_SYS++) R9 ← *(SP_SYS++) R8 ← *(SP_SYS++) SREG[L] ← 0; else SR ← RSR_Current Context PC ← RAR_Current Context SREG[L] ← 0;

Syntax:

I RETE

Operands:

None

Status Flags

Q: Not affected V: Not affected N: Not affected Z: Not affected C: Not affected

AVR32

Opcode: 15 9 8 4 3 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1

32000D–04/2011 ATMEL® 307

RETJ – Return from Java trap

Description Returns from a Java trap.

Operation: I. PC \leftarrow LR; J \leftarrow 1; R \leftarrow 0; if ( SR[M2:M0] == B'001 ) GM \leftarrow 0;

Syntax: I retj

Operands: None

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: \begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & & & & & & & & & 9 & 8 & & & & 4 & 3 & & & & 0 \ \hline 1 & 1 & 0 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 1 & 1 \ \hline \end{tabular}

308 AVR32 32000D–04/2011

AVR32

RETS – Return from supervisor call

Description Returns from a supervisor call.

Operation: I. If ( SR[M2:M0] == B'000 ) Issue Privilege Violation Exception; else if ( SR[M2:M0] == B'001 ) If (microarchitecture == AVR32A) SR \leftarrow *(SP${SYS}$++) PC \leftarrow *(SP${SYS}$++) else SR \leftarrow RSR${SUP}$; PC \leftarrow RAR${SUP}$; else PC \leftarrow LR$_{Current Context}$

Syntax: I RETS

Operands: None

Status Flags Q: Not affected V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode: 15 9 8 4 3 0 | 1 1 0 1 0 1 1 | 0 0 0 0 1 | 0 0 1 1 |

32000D-04/2011 ATMEL 309

RETSS – Return from Secure State

Architecture revision 3 and higher.

Description Returns from Secure State.

Operation: I. If ( SR[SS] == 0 ) Issue Privilege Violation Exception; else SR \leftarrow SS_RSR PC \leftarrow SS_RAR

Syntax: I RETSS

Operands: None

Status Flags Q: Not affected V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode: 15 9 8 4 3 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 |

310 AVR32 32000D–04/2011

RJMP – Relative Jump

Description Jump the specified amount relative to the Program Counter .

Operation: I. PC \leftarrow PC + (SE(disp10)<<1);

Syntax: I. rjmp PC[disp]

Operands: I. disp \in {-1024, -1022, ..., 1022}

Status Flags Q: Not affected V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & & 13 & 12 & 11 & & & & & & & & 4 & 3 & 2 & 1 & 0 \ \hline 1 & 1 & 0 & 0 & \multicolumn{9}{c|}{disp10[7:0]} & 1 & 0 & \multicolumn{2}{c|}{disp10[9:8]} \ \hline \end{tabular}

32000D–04/2011 ATMEL 311

ROL – Rotate Left through Carry

Description Shift all bits in Rd one place to the left. The C flag is shifted into the LSB. The MSB is shifted into the C flag.

Operation: I. C' ← Rd[31]; Rd ← Rd << 1; Rd[0] ← C; C ← C';

Syntax: I. rol Rd

Operands: I. d ∈ {0, 1, ..., 15}

Status Flags: Q: Not affected V: Not affected N: N ← Res[31] Z: Z ← (RES[31:0] == 0) C: C ← Rd[31]

Opcode: 312 AVR32 32000D–04/2011

ROR – Rotate Right through Carry

Description Shift all bits in Rd one place to the right. The C flag is shifted into the MSB. The LSB is shifted into the C flag.

Operation: I. C' \leftarrow Rd[0]; Rd \leftarrow Rd >> 1; Rd[31] \leftarrow C; C \leftarrow C';

Syntax: I. ror Rd

Operands: I. d \in {0, 1, ..., 15}

Status Flags: Q: Not affected V: Not affected N: N \leftarrow Res[31] Z: Z \leftarrow (RES[31:0] == 0) C: C \leftarrow Rd[0]

Opcode: \begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & & 13 & 12 & & & & 9 & 8 & & & & 4 & 3 & & 0 \ \hline 0 & 1 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & \multicolumn{4}{c|}{Rd} \ \hline \end{tabular}

32000D–04/2011 ATMEL® 313

RSUB – Reverse Subtract

Description

Performs a subtraction and stores the result in destination register. Similar to sub, but the minuend and subtrahend are interchanged.

Operation:

I. Rd ← Rs - Rd; II. Rd ← SE(imm8) - Rs;

Syntax:

I. rsub Rd, Rs II. rsub Rd, Rs, imm

Operands:

I. {d, s} ∈ {0, 1, ..., 15} II. {d, s} ∈ {0, 1, ..., 15} imm ∈ {-128, -127, ..., 127}

Status Flags:

Format I: OP1 = Rs, OP2 = Rd Format II: OP1 = SE(imm8), OP2 = Rs Q: Not affected V: V ← (OP1[31] ∧ ¬OP2[31] ∧ ¬RES[31]) ∨ (¬OP1[31] ∧ OP2[31] ∧ RES[31]) N: N ← RES[31] Z: Z ← (RES[31:0] == 0) C: C ← ¬OP1[31] ∧ OP2[31] ∨ OP2[31] ∧ RES[31] ∨ ¬OP1[31] ∧ RES[31]

Opcode:

Format I:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & \multicolumn{3}{c|}{13} & \multicolumn{4}{c|}{12 \hspace{1em} 9} & \multicolumn{1}{c|}{8} & \multicolumn{4}{c|}{4 \hspace{1em} 3} & \multicolumn{3}{c|}{0} \ \hline 0 & 0 & 0 & \multicolumn{4}{c|}{Rs} & 0 & 0 & 0 & 1 & 0 & \multicolumn{3}{c|}{Rd} \ \hline \end{tabular}

Format II:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 31 & \multicolumn{3}{c|}{29} & \multicolumn{4}{c|}{28 \hspace{1em} 25} & \multicolumn{1}{c|}{24} & \multicolumn{4}{c|}{20 \hspace{1em} 19} & \multicolumn{3}{c|}{16} \ \hline 1 & 1 & 1 & \multicolumn{4}{c|}{Rs} & 0 & 0 & 0 & 0 & 0 & \multicolumn{3}{c|}{Rd} \ \hline \end{tabular}

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & \multicolumn{3}{c|}{12} & \multicolumn{1}{c|}{11} & \multicolumn{4}{c|}{8 \hspace{1em} 7} & \multicolumn{8}{c|}{0} \ \hline 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & \multicolumn{8}{c|}{imm8} \ \hline \end{tabular}

AVR32

RSUB{cond4} – Conditional Reverse Subtract

Architecture revision: Architecture revision 2 and higher.

Description Performs a subtraction and stores the result in destination register. Similar to sub, but the minuend and subtrahend are interchanged.

Operation: I. if ( cond4) Rd \leftarrow SE(imm8) - Rd;

Syntax: I. rsub{cond4} Rd, imm

Operands: I. d \in {0, 1, ..., 15} cond4 \in {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} imm \in {-128, -127, ..., 127}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | Rd | 15 12 11 8 7 0 | 0 | 0 | 0 | 0 | cond4 | imm8 |

32000D-04/2011 ATMEL 315

SATADD.H – Saturated Add of Halfwords

Description Adds the two halfword registers specified and stores the result in destination register. The result is saturated if it overflows the range representable with 16 bits. If saturation occurs, the Q flag is set.

Operation: I. temp \leftarrow ZE(Rx[15:0]) + ZE(Ry[15:0]); if (Rx[15] \land Ry[15] \land \negtemp[15]) \lor (\negRx[15] \land \negRy[15] \land temp[15]) then if Rx[15] == 0 then Rd \leftarrow 0x00007fff; else Rd \leftarrow 0xffff8000; else Rd \leftarrow SE(temp[15:0]);

Syntax: I. satadd.hRd, Rx, Ry

Operands: I. {d, x, y} \in {0, 1, ..., 15}

Status Flags: Q: Q \leftarrow (Rx[15] \land Ry[15] \land \negtemp[15]) \lor (\negRx[15] \land \negRy[15] \land temp[15]) \lor Q V: V \leftarrow (Rx[15] \land Ry[15] \land \negtemp[15]) \lor (\negRx[15] \land \negRy[15] \land temp[15]) N: N \leftarrow Rd[15] Z: Z \leftarrow if (Rd[15:0] == 0) C: C \leftarrow 0

Opcode: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 | 0 | 0 | 0 | 0 | Ry | 15 12 11 4 3 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | Rd |

316 AVR32 32000D–04/2011

SATADD.W– Saturated Add of Words

Description

Adds the two registers specified and stores the result in destination register. The result is saturated if a two's complement overflow occurs. If saturation occurs, the Q flag is set.

Operation:

I. temp \leftarrow Rx + Ry; if (Rx[31] \wedge Ry[31] \wedge ¬temp[31]) \vee (¬Rx[31] \wedge ¬Ry[31] \wedge temp[31]) then if Rx[31] == 0 then Rd \leftarrow 0x7fffffff; else Rd \leftarrow 0x8000000; else Rd \leftarrow temp;

Syntax:

I. satadd.wRd, Rx, Ry

Operands:

I. {d, x, y} \in {0, 1, ..., 15}

Status Flags:

Q: Q \leftarrow (Rx[31] \wedge Ry[31] \wedge ¬temp[31]) \vee (¬Rx[31] \wedge ¬Ry[31] \wedge temp[31]) \vee Q V: V \leftarrow (Rx[31] \wedge Ry[31] \wedge ¬temp[31]) \vee (¬Rx[31] \wedge ¬Ry[31] \wedge temp[31]) N: N \leftarrow Rd[31] Z: Z \leftarrow (Rd[31:0] == 0) C: C \leftarrow 0

Opcode:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \multicolumn{1}{c}{31} & \multicolumn{1}{c}{29} & \multicolumn{1}{c}{28} & \multicolumn{4}{c}{25} & \multicolumn{1}{c}{24} & \multicolumn{5}{c}{20} & \multicolumn{1}{c}{19} & \multicolumn{4}{c}{16} \ \hline 1 & 1 & 1 & \multicolumn{4}{c|}{Rx} & 0 & 0 & 0 & 0 & 0 & \multicolumn{1}{c|}{Ry} & \multicolumn{4}{c}{} \ \hline \multicolumn{1}{c}{15} & \multicolumn{1}{c}{12} & \multicolumn{1}{c}{11} & \multicolumn{8}{c}{4} & \multicolumn{1}{c}{3} & \multicolumn{4}{c}{0} \ \hline 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & \multicolumn{1}{c|}{Rd} & \multicolumn{4}{c}{} \ \hline \end{tabular}

32000D-04/2011 ATMEL 317

SATRNDS – Saturate with Rounding Signed

Description

This instruction considers the value in (Rd>>sa)[bp-1:0] as a signed value. Rounding is performed after the shift. If the value in (Rd>>sa)[31:bp] is not merely a sign-extention of this value, overflow has occurred and saturation is performed to the maximum signed positive or negative value. If saturation occurs, the Q flag is set. An arithmetic shift is performed on Rd. If bp equals zero, no saturation is performed.

Operation:

I. Temp \leftarrow Rd >> sa if (sa != 0) Rnd = Rd[sa-1] Temp = Temp + Rnd; if ((Temp == SE( Temp[bp-1:0])) || (bp == 0) ) Rd \leftarrow Temp; else if (Temp[31] == 1) Rd \leftarrow -2$^{bp-1}$; else Rd \leftarrow 2$^{bp-1}$ - 1;

Syntax:

I. satrnds Rd >> sa, bp

Operands:

I. d \in {0, 1, ..., 15} {sa, bp} \in {0, 1, ..., 31}

Status Flags:

Q: Set if saturation occurred or Q was already set, cleared otherwise. V: Not affected N: Not affected Z: Not affected C: Not affected

Opcode:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline \multicolumn{4}{|c|}{31 \quad 29} & \multicolumn{4}{|c|}{28 \quad 25} & \multicolumn{4}{|c|}{24 \quad 20} & \multicolumn{4}{|c|}{19 \quad 16} \ \hline 1 & 1 & 1 & 1 & 0 & 0 & 1 & 1 & 1 & 0 & 1 & 1 & \multicolumn{4}{|c|}{Rd} \ \hline \end{tabular}

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline \multicolumn{4}{|c|}{15 \quad 12} & \multicolumn{2}{|c|}{11 \quad 10} & \multicolumn{1}{|c|}{9} & \multicolumn{5}{|c|}{5 \quad 4} & \multicolumn{4}{|c|}{0} \ \hline 0 & 0 & 0 & 0 & 0 & 0 & \multicolumn{5}{|c|}{bp} & \multicolumn{4}{|c|}{sa} \ \hline \end{tabular}