Atmel AVR32 user guide: MIN – Return Minimum Value

AVR32

MFSR – Move from System Register

Description The instruction copies the value in the specified system register to the specified register in the register file. Note that special timing concerns must be considered when operating on the system registers, see the Pipeline Chapter for details.

Operation: I. Rd \leftarrow SystemRegister[SystemRegisterAddress << 2];

Syntax: I. mfsr Rd, SystemRegisterAddress

Operands: I. SystemRegisterAddress \in {0, 4, 8, ..., 1020}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Note: Some system registers are implementation defined. If accessing a system register that does not exist, the result is UNDEFINED.

With the exception of accessing the JECR and JOSP system registers, this instruction can only be executed in a privileged mode. Execution from any other mode will trigger a Privilege Violation exception.

JECR and JOSP can be accessed from all modes with this instruction.

MIN – Return Minimum Value

Description Sets Rd equal to the signed minimum of Rx and Ry.

Operation: I. If Rx < Ry Rd \leftarrow Rx; else Rd \leftarrow Ry;

Syntax: I. min Rd, Rx, Ry

Operands: d, x, y \in {0, 1, ..., 15}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 0 0 0 0 | Rd | | 0 | 0 | 0 | 0 | 1 1 0 1 0 1 0 0 | Rd | 15 12 11 4 3 0

222 AVR32 32000D-04/2011

AVR32

MOV – Move Data Into Register

Description

Moves a value into a register. The value may be an immediate or the contents of another register. Note that Rd may specify PC, resulting in a jump. All flags are unchanged.

Operation:

I. Rd \leftarrow SE(imm8); II. Rd \leftarrow SE(imm21); III. Rd \leftarrow Rs;

Syntax:

I. mov Rd, imm II. mov Rd, imm III. mov Rd, Rs

Operands:

I. d \in {0, 1, ..., 15} imm \in {-128, -127, ..., 127} II. d \in {0, 1, ..., 15} imm \in {-1048576, -104875, ..., 1048575} III. d, s \in {0, 1, ..., 15}

Status Flags:

Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

Format I: Format II:

32000D-04/2011 ATMEL® 223

Format III:

224 AVR32 32000D–04/2011

MOV{cond4} – Conditional Move Register

Description Copies the contents of the source register or immediate to the destination register. The source register is unchanged. All flags are unchanged.

Operation: I. if ( cond4) Rd \leftarrow Rs; II. if ( cond4) Rd \leftarrow SE(imm8);

Syntax: I. mov{cond4} Rd, Rs II. mov{cond4} Rd, imm

Operands: I. {d, s} \in {0, 1, ..., 15} cond4 \in {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} II. d \in {0, 1, ..., 15} cond4 \in {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt, le, hi, vs, vc, qs, al} imm \in {-128, -127, ..., 127}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: 31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rs | 0 0 0 0 0 | Rd | 15 12 11 8 7 4 3 0 | 0 | 0 | 0 | 1 | 0 1 1 1 | cond4 | 0 0 0 0 |

32000D-04/2011 ATMEL 225

Format II:

MOVH – Move Data Into High Halfword of Register

Architecture revision:

Architecture revision 2 and higher.

Description

Moves a value into the high halfword of a register. The low halfword is cleared. All flags are unchanged.

Operation:

I. Rd ← imm16<<16;

Syntax:

I. movh Rd, imm

Operands:

I. d ∈ {0, 1, ..., 15} imm ∈ {0, 1, ..., 65535}

Status Flags:

Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

MTDR – Move to Debug Register

Description

The instruction copies the value in the specified register to the specified debug register. Note that special timing concerns must be considered when operating on the system registers, see the Pipeline Chapter for details.

Operation:

I. DebugRegister[DebugRegisterAddress << 2] \leftarrow Rs;

Syntax:

I. mtdr DebugRegisterAddress, Rs

Operands:

I. DebugRegisterAddress \in {0, 4, 8, ..., 1020}

Status Flags:

Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

Note: The debug registers are implementation defined, and updates of these registers are handled in an implementation specific way.

This instruction can only be executed in a privileged mode. Execution from any other mode will trigger a Privilege Violation exception.

AVR32

MTSR – Move to System Register

Description The instruction copies the value in the specified register to the specified system register. Note that special timing concerns must be considered when operating on the system registers, see the Implementation Manual for details.

Operation: I. SystemRegister[SystemRegisterAddress << 2] \leftarrow Rs;

Syntax: I. mtsr SystemRegisterAddress, Rs

Operands: I. SystemRegisterAddress \in {0, 4, 8, ..., 1020}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Note: Some system registers are implementation defined. If writing a system register that does not exist, or to a register that is read only, the instruction is executed but no registers are updated.

With the exception of accessing the JECR and JOSP system registers, this instruction can only be executed in a privileged mode. Execution from any other mode will trigger a Privilege Violation exception. JECR and JOSP can be accessed from all modes with this instruction.

The instruction mtsr JOSP, Rx must be used with care. The programmer must ensure that no change of flow instruction nor an INCJOSP instruction follows mtsr JOSP, Rx within a number of instructions. This number of cycles is implementation defined. It should also be noted, that this is true even if the instructions are not to be executed. For instance the sequence

mtsr JOSP, Rx retj incjosp

32000D-04/2011 ATMEL 229

will execute with an incorrect result. In practice this warning will only affect programmers writing their own Java Virtual Machine based on the AVR32 Java Extension module.

230 AVR32 32000D–04/2011

MUL – Multiply

Description Multiplies the specified operands and stores the result in the destination register.

Operation: I. Rd ← Rd × Rs; II. Rd ← Rx × Ry; III. Rd ← Rs × SE(imm8)

Syntax: I. mul Rd, Rs II. mul Rd, Rx, Ry III. mul Rd, Rs, imm

Operands: I. {d, s} ∈ {0, 1, ..., 15} II. {d, x, y} ∈ {0, 1, ..., 15} III. {d, s} ∈ {0, 1, ..., 15} imm ∈ {-128, -127, ..., 127}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Format I: 15 13 12 9 8 4 3 0 ┌───┬───┬───────────────┬───┬───────────────┬───┬───────────────┐ │ 1 │ 0 │ 1 │ Rs│ 1 0 0 1 │ 1 │ │ └──────┴───────────────┴───┴───────────────┴──────────────────┘ Rd

Format II: 31 29 28 25 24 20 19 16 ┌──────┬──────────────┬───┬───┬───┬───┬───┬───┬───┬───────────┬───┬───┬───┐ │ 1 │ 1 │ 1 │ │ Rx│ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ │ Ry│ │ │ └───┴───┴───┴───────────┴───┴───┴───┴───┴──────┴──────────────┴───┴───┴───┘ 15 12 11 4 3 0 ┌──────┬──────────────────┬───┬───┬───┬───┬───┬───┬───┬───────────────┐ │ 0 │ 0 │ 0 │ 0 │ 0 │ 0 │ 1 │ 0 │ 0 │ 1 │ 0 │ 0 │ Rd│ └───┴───┴───┴───────────────┴──────┴──────┴──────┴──────────────────┘

32000D-04/2011 ATMEL® 231

Format III:

MULHH.W – Multiply Halfword with Halfword

Description Multiplies the two halfword registers specified and stores the result in the destination word-register. The halfword registers are selected as either the high or low part of the operand registers.

Operation: I. If (Rx-part == t) then operand1 = SE(Rx[31:16]) else operand1 = SE(Rx[15:0]); If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]); Rd \leftarrow operand1 × operand2;

Syntax: I. mulhh.w Rd, Rx:, Ry:

Operands: I. {d, x, y} \in {0, 1, ..., 15} part \in {t,b}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: Example: mulhh.wR10, R2:t, R3:b will perform R10 \leftarrow SE(R2[31:16]) × SE(R3[15:0])

32000D-04/2011 ATMEL 233

MULNHH.W – Multiply Halfword with Negated Halfword

Description

Multiplies the two halfword registers specified and stores the result in the destination word-register. The halfword registers are selected as either the high or low part of the operand registers. The result is negated.

Operation:

I. If (Rx-part == t) then operand1 = SE(Rx[31:16]) else operand1 = SE(Rx[15:0]); If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]); Rd ← - (operand1 × operand2);

Syntax:

I. mulnhh.w Rd, Rx:, Ry:

Operands:

I. {d, x, y} ∈ {0, 1, ..., 15} part ∈ {t,b}

Status Flags:

Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

234 AVR32 32000D-04/2011

MULNWH.D – Multiply Word with Negated Halfword

Description

Multiplies the word register with the halfword register specified and stores the negated result in the destination register pair. The halfword register is selected as either the high or low part of Ry. Since the most significant part of the product is stored, no overflow will occur.

Operation:

I. operand1 = Rx; If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]); (Rd+1:Rd)[63:16] \leftarrow - (operand1 × operand2); Rd[15:0] \leftarrow 0;

Syntax:

I. mulnwh.d Rd, Rx, Ry:

Operands:

I. d \in {0, 2, 4, ..., 14} {x, y} \in {0, 1, ..., 15} part \in {t,b}

Status Flags:

Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

32000D-04/2011 235

MULS.D – Multiply Signed

Description Multiplies the two registers specified and stores the result in the destination registers.

Operation: I. Rd+1:Rd ← Rx × Ry;

Syntax: I. muls.d Rd, Rx, Ry

Operands: I. d ∈ {0, 2, 4, ..., 14} {x, y} ∈ {0, 1, ..., 15}

Status Flags Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 0 0 0 0 | Ry | 15 12 11 4 3 0 | 0 0 0 0 | 0 1 0 0 0 1 0 0 | Rd |

236 AVR32 32000D–04/2011

MULSATHH.H – Multiply Halfwords with Saturation into Halfword

Description Multiplies the two halfword registers specified, shifts the results one position to the left and stores the sign-extended high halfword of the result in the destination word-register. If the two operands equals -1, the result is saturated to the largest positive 16-bit fractional number. The halfword registers are selected as either the high or low part of the operand registers.

Operation: I. If (Rx-part == t) then operand1 = SE(Rx[31:16]) else operand1 = SE(Rx[15:0]); If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]); If (operand1 == operand2 == 0x8000) Rd \leftarrow 0x7FFF; else Rd \leftarrow SE( (operand1 × operand2) >> 15 );

Syntax: I. mulsathh.h Rd, Rx:, Ry:

Operands: I. {d, x, y} \in {0, 1, ..., 15} part \in {t,b}

Status Flags: Q: Set if saturation occurred, or previously set. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

Example: mulsathh.h R10, R2:t, R3:b will perform R10 \leftarrow SE( Sat(SE(R2[31:16]) × SE(R3[15:0]) ) >> 15 )

ATMEL® 32000D–04/2011 237

MULSATHH.W – Multiply Halfwords with Saturation into Word

Description

Multiplies the two halfword registers specified, shifts the results one position to the left and stores the result in the destination word-register. If the two operands equals -1, the result is saturated to the largest positive 32-bit fractional number. The halfword registers are selected as either the high or low part of the operand registers.

Operation:

I. If (Rx-part == t) then operand1 = SE(Rx[31:16]) else operand1 = SE(Rx[15:0]); If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]); If (operand1 == operand2 == 0x8000) Rd \leftarrow 0x7FFF_FFFF; else Rd \leftarrow (operand1 × operand2) << 1;

Syntax:

I. mulsathh.w Rd, Rx:, Ry:

Operands:

I. {d, x, y} \in {0, 1, ..., 15} part \in {t,b}

Status Flags:

Q: Set if saturation occurred, or previously set. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 31 & & 29 & 28 & & & & & 25 & 24 & & & & & & & 20 & 19 & & & & 16 & & & & & & & & & & \ \hline 1 & & 1 & 1 & \multicolumn{4}{c|}{Rx} & \multicolumn{5}{c|}{0 0 0 0 0} & \multicolumn{4}{c|}{Ry} & \ \hline 15 & & & & 12 & 11 & & & 8 & 7 & 6 & 5 & 4 & 3 & & & & & & & 0 & & & & & & & & & & \ \hline 0 & & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 1 & 0 & X & Y & \multicolumn{4}{c|}{Rd} & \ \hline \end{tabular}

Example:

mulsathh.w R10, R2:t, R3:b will perform R10 \leftarrow Sat( (SE(R2[31:16]) × SE(R3[15:0] )) << 1)

AVR32

MULSATRNDHH.H – Multiply Halfwords with Saturation and Rounding into Halfword

Description

Multiplies the two halfword registers specified, shifts the results one position to the left and stores the result in the destination word-register. If the two operands equal -1, the result is saturated to the largest positive 16-bit fractional number. The halfword registers are selected as either the high or low part of the operand registers. The product is rounded.

Operation:

I. If (Rx-part == t) then operand1 = SE(Rx[31:16]) else operand1 = SE(Rx[15:0]); If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]); If (operand1 == operand2 == 0x8000) Rd \leftarrow 0x7FFF; else Rd \leftarrow SE( ((operand1 × operand2) + 0x4000 ) >> 15 );

Syntax:

I. mulsatrndhh.h Rd, Rx:, Ry:

Operands:

I. {d, x, y} \in {0, 1, ..., 15} part \in {t,b}

Status Flags:

Q: Set if saturation occurred, or previously set. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | | | | | Rx | | | | | | | 0 | 0 | 0 | 0 | 0 | | | | | | | | | | Ry | | | | | 15 12 11 8 7 6 5 4 3 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | X | Y | | | | | | | | | | | | | | | | | | | | | | Rd | | | | |

Example: mulsatrndhh.h R10, R2:t, R3:b will perform R10 \leftarrow SE( Sat( SE(R2[31:16]) × SE(R3[15:0]) ) + 0x4000) >> 15)

32000D-04/2011 ATMEL 239

MULSATRNDWH.W – Multiply Word and Halfword with Saturation and Rounding into Word

Description

Multiplies the word register with the halfword register specified, rounds the upper 32 bits of the result and stores it in the destination word-register. The halfword register is selected as either the high or low part of Ry. Since the most significant part of the product is stored, no overflow will occur. If the two operands equals -1, the result is saturated to the largest positive 32-bit fractional number.

Operation:

I. operand1 = Rx; If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]); If ((operand1 == 0x8000_0000) && (operand2 == 0x8000)) Rd \leftarrow 0x7FFF_FFFF; else Rd \leftarrow SE( (operand1 × operand2) + 0x4000 ) >> 15 );

Syntax:

I. mulsatrndwh.w Rd, Rx, Ry:

Operands:

I. {d, x, y} \in {0, 1, ..., 15} part \in {t,b}

Status Flags:

Q: Set if saturation occurred, or previously set. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

• \begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c ........ } \end{tabular}

Example: mulsatrndwh.w R10, R2, R3b will perform R10 \leftarrow (Sat( R2[31:16] × SE(R3[15:0]) ) + 0x4000) >> 15

240 AVR32 32000D-04/2011

AVR32

MULSATWH.W – Multiply Word and Halfword with Saturation into Word

Description Multiplies the word register with the halfword register specified and stores the upper 32 bits of the result in the destination word-register. The halfword register is selected as either the high or low part of Ry. Since the most significant part of the product is stored, no overflow will occur. If the two operands equal -1, the result is saturated to the largest positive 32-bit fractional number.

Operation: I. operand1 = Rx; If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]); If ((operand1 == 0x8000_0000) && (operand2 == 0x8000)) Rd \leftarrow 0x7FFF_FFFF; else Rd \leftarrow (operand1 × operand2) >> 15;

Syntax: I. mulsatwh.w Rd, Rx, Ry:

Operands: I. {d, x, y} \in {0, 1, ..., 15} part \in {t,b}

Status Flags: Q: Set if saturation occurred, or previously set. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

• \begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c ........ } \hline
• 31 & & 29 & 28 & & & & & & & 25 & 24 & & & & & & & & & & 20 & 19 & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & ........ \ \hline 1 & & 1 & 1 & \multicolumn{4}{c|}{Rx} & \multicolumn{5}{c|}{0 0 0 0 0} & \multicolumn{4}{c|}{Ry} \ \hline
• 15 & & & & & & & & 12 & 11 & & & & & & & & & & & & 8 & 7 & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & ........

MULU.D – Multiply Unsigned

Description Multiplies the two registers specified and stores the result in the destination registers.

Operation: I. Rd+1:Rd ← Rx × Ry;

Syntax: I. mulu.d Rd, Rx, Ry

Operands: I. d ∈ {0, 2, 4, ..., 14} {x, y} ∈ {0, 1, ..., 15}

Status Flags Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

31 29 28 25 24 20 19 16 | 1 | 1 | 1 | Rx | 0 0 0 0 0 | Rd | 15 12 11 4 3 0 | 0 0 0 0 | 0 1 1 0 0 1 0 0 | Rd |

242 AVR32 32000D–04/2011

MULWH.D – Multiply Word with Halfword

Description Multiplies the word register with the halfword register specified and stores result in the destination register pair. The halfword register is selected as either the high or low part of Ry. Since the most significant part of the product is stored, no overflow will occur.

Operation: I. operand1 = Rx; If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]); (Rd+1:Rd)[63:16] \leftarrow operand1 × operand2; Rd[15:0] \leftarrow 0;

Syntax: I. mulwh.d Rd, Rx, Ry:

Operands: I. d \in {0, 2, 4, ..., 14} {x, y} \in {0, 1, ..., 15} part \in {t,b}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

32000D-04/2011 ATMEL 243

MUSFR – Copy Register to Status Register

Description The instruction copies the lower 4 bits of the register Rs to the lower 4 bits of the status register.

Operation: I. SR[3:0] \leftarrow Rs[3:0];

Syntax: I. musfr Rs

Operands: I. s \in {0, 1, ..., 15}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode:

\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & \multicolumn{2}{c|}{13} & \multicolumn{2}{c|}{12} & \multicolumn{4}{c|}{9} & \multicolumn{1}{c|}{8} & \multicolumn{4}{c|}{4} & \multicolumn{2}{c|}{3} & 0 \ \hline 0 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 1 & 1 & \multicolumn{2}{c|}{Rs} \ \hline \end{tabular}

244 AVR32 32000D–04/2011

MUSTR – Copy Status Register to Register

Description The instruction copies the value of the 4 lower bits of the status register into the register Rd. The value is zero extended.

Operation: I. Rd \leftarrow ZE(SR[3:0]);

Syntax: I. mustr Rd

Operands: I. d \in {0, 1, ..., 15}

Status Flags: Q: Not affected. V: Not affected. N: Not affected. Z: Not affected. C: Not affected.

Opcode: \begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} \hline 15 & \multicolumn{2}{c|}{13} & 12 & \multicolumn{4}{c|}{9} & 8 & \multicolumn{4}{c|}{4} & 3 & \multicolumn{2}{c}{0} \ \hline 0 & 1 & 0 & 1 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 1 & 0 & \multicolumn{3}{c}{Rd} \ \hline \end{tabular}

32000D-04/2011 ATMEL 245