Latest threads in Field-Programmable Gate Arrays

Can I store the output of my FPGA logic inside FPGA memory for debug data values?

Hi, I am using altera FPGA. How can I put the output of my logic into the FPGA internal memories(assuming I have unused...

6 18yrs

bajajk

6 18yrs bajajk

Help Needed - LPC Bus Interface

I've problem with my codes. I'm trying to make a LPC Bus interface with my Spartan 3E to tap the bus traffic coming fro...

0 18yrs

me75

0 18yrs me75

Help =(

I've problem with my codes. I'm trying to make a LPC Bus interface with my Spartan 3E to tap the bus traffic coming fro...

0 18yrs

me75

0 18yrs me75

JTAG IR length detection

We are currently building a board at work that will have connectors for X number of boards (that is between 0 and the n...

6 18yrs

slide.o.mix

6 18yrs slide.o.mix

How can I create a direct FSL connection?

Hi all ... I'm new to using Xilinx's EDK (version 10.1.02) and could use a little help. I'd like to create a direct FSL...

0 18yrs

james

0 18yrs james

EBAY: XC2V1000-5FG456C

FYI: http://tinyurl.com/6h6dqu -Martin

8 18yrs

martin.usenet

8 18yrs martin.usenet

2 BUFIOs in the same clock-capable pair?

I have 2 clock inputs coming into the FPGA through a clock-capable IO pair (AN19 and AN20). The clock inputs are of the...

2 18yrs

petersen.curt

2 18yrs petersen.curt

How do I send data and receive data from the FPGA and simulink/matlab

Hi all, I am using Altera DSP Builder to implement an OFDM receiver. I am working on Stratix II Altera FPGA.I need to s...

0 18yrs

natarajan.jayaram

0 18yrs natarajan.jayaram

How to download bitstream into Cyclone III starter board

Hi All, I am migrating from Spartan 3e to Cyclone III. We bought only cyclone II starter board. We don't have any USB b...

3 18yrs

shankaran.siva7

3 18yrs shankaran.siva7

Spartan 3E I/O Pins -- LPC Bus Interface

Im trying to make a LPC bus interface to record the bus traffic as a result of keypresses. Im using the clk from the LP...

1 18yrs

me75

1 18yrs me75

Altera FPGA and data from matlab workspace.

Hey, I need to send some data to the Altera Stratix II FPGA board from the matlab workspace and then do some FFT, FIR p...

2 18yrs

natarajan.jayaram

2 18yrs natarajan.jayaram

What's wrong with this Virtex4 DCM?

I'm using the DCM instantiation reported below, on a Virtex4fx60 target. I have two different boards (ICS-8550) the dif...

4 18yrs

gnemesis2001

4 18yrs gnemesis2001

SBC with ADC, 1GE, and SATA2?

I'm lokking for a small (4x6", 6x8", range) SBC that has a reasonably good A/D converter (100+MSPS), at least one 1G et...

2 18yrs

mikemac

2 18yrs mikemac

Virtex 4 expected production end-of-life

Is there any information about the expected purchase lifetime for the Virtex-4 series, specifically the FX12? We've bee...

7 18yrs

nobby

7 18yrs nobby

Understanding PPC405 execution.

Hi all. I'm trying to figure out how much time does it take for a such code to execute. I'm using modelsim on ppc405 pr...

0 18yrs

mariusz.grad

0 18yrs mariusz.grad

Field-Programmable Gate Arrays

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