Field-Programmable Gate Arrays

Help =(

I've problem with my codes. I'm trying to make a LPC Bus interface with my Spartan 3E to tap the bus traffic coming fro...

0 comments posted 18yrs

posted by me75

0 comments posted 18yrs posted by me75

JTAG IR length detection

We are currently building a board at work that will have connectors for X number of boards (that is between 0 and the n...

6 comments posted 18yrs

posted by slide.o.mix

6 comments posted 18yrs posted by slide.o.mix

How can I create a direct FSL connection?

Hi all ... I'm new to using Xilinx's EDK (version 10.1.02) and could use a little help. I'd like to create a direct FSL...

0 comments posted 18yrs

posted by james

0 comments posted 18yrs posted by james

EBAY: XC2V1000-5FG456C

FYI: http://tinyurl.com/6h6dqu -Martin

8 comments posted 18yrs

posted by martin.usenet

8 comments posted 18yrs posted by martin.usenet

2 BUFIOs in the same clock-capable pair?

I have 2 clock inputs coming into the FPGA through a clock-capable IO pair (AN19 and AN20). The clock inputs are of the...

2 comments posted 18yrs

posted by petersen.curt

2 comments posted 18yrs posted by petersen.curt

How do I send data and receive data from the FPGA and simulink/matlab

Hi all, I am using Altera DSP Builder to implement an OFDM receiver. I am working on Stratix II Altera FPGA.I need to s...

0 comments posted 18yrs

posted by natarajan.jayaram

0 comments posted 18yrs posted by natarajan.jayaram

How to download bitstream into Cyclone III starter board

Hi All, I am migrating from Spartan 3e to Cyclone III. We bought only cyclone II starter board. We don't have any USB b...

3 comments posted 18yrs

posted by shankaran.siva7

3 comments posted 18yrs posted by shankaran.siva7

Spartan 3E I/O Pins -- LPC Bus Interface

Im trying to make a LPC bus interface to record the bus traffic as a result of keypresses. Im using the clk from the LP...

1 comments posted 18yrs

posted by me75

1 comments posted 18yrs posted by me75

Altera FPGA and data from matlab workspace.

Hey, I need to send some data to the Altera Stratix II FPGA board from the matlab workspace and then do some FFT, FIR p...

2 comments posted 18yrs

posted by natarajan.jayaram

2 comments posted 18yrs posted by natarajan.jayaram

What's wrong with this Virtex4 DCM?

I'm using the DCM instantiation reported below, on a Virtex4fx60 target. I have two different boards (ICS-8550) the dif...

4 comments posted 18yrs

posted by gnemesis2001

4 comments posted 18yrs posted by gnemesis2001

SBC with ADC, 1GE, and SATA2?

I'm lokking for a small (4x6", 6x8", range) SBC that has a reasonably good A/D converter (100+MSPS), at least one 1G et...

2 comments posted 18yrs

posted by mikemac

2 comments posted 18yrs posted by mikemac

Virtex 4 expected production end-of-life

Is there any information about the expected purchase lifetime for the Virtex-4 series, specifically the FX12? We've bee...

7 comments posted 18yrs

posted by nobby

7 comments posted 18yrs posted by nobby

Understanding PPC405 execution.

Hi all. I'm trying to figure out how much time does it take for a such code to execute. I'm using modelsim on ppc405 pr...

0 comments posted 18yrs

posted by mariusz.grad

0 comments posted 18yrs posted by mariusz.grad

Help to SImulate Uart TX

I'm using the following code. I've managed to make it work on my fpga before. but when I try to simulate on my modelsim...

7 comments posted 18yrs

posted by me75

7 comments posted 18yrs posted by me75

QPSK SymbolRate generator ...

I have built a QPSK modulator, but I have some doubts about the generation of SymbolRate variable. The SymbolRate range...

7 comments posted 18yrs

posted by 78kappa78(at)virgilio(dot)it

7 comments posted 18yrs posted by 78kappa78(at)virgilio(dot)it