Spartan 3E I/O Pins -- LPC Bus Interface

Im trying to make a LPC bus interface to record the bus traffic as a result of keypresses.

Im using the clk from the LPC bus as my process clock. But it seems that the LFRAME# signal is always high and never drop low.

Im using the Expansion Connectors I/Os, accessory headers, on the spartan 3e fpga to do the probing.

I'm not sure if the I/O pins Im using is appropriate. I'm using the J4 and J1 6-pin accessory header on the board to probe... with LVTTL as my I/O standard.

Is it fast enough? cause the result of my output does not look like it is appearing fast enough

Anyone has any idea what else I can do?

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I've changed the stuffs slightly.

I'm using the LCLK from the bus and the FPGA 50Mhz clock for my processes. I'm using those expansion connectors to probe the bus, storing it into a 2-clock FIFO, and a uart which reads from the FIFO and send it to the PC

I've simulated it on my modelsim and it come out as desired, but when I try out on the actual thing...the uart data is weird.

I've modified my code to only allow 2 kind of data to be sent out. "00000000" will be sent out every 13 cycles, while during the 13 cycles it will be the other set of data, "01111111". However the data I collected doesnt appear to be so.

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