What's wrong with this Virtex4 DCM?

I'm using the DCM instantiation reported below, on a Virtex4fx60 target. I have two different boards (ICS-8550) the differ only for the ruggedization level, the boards are almost the same and so should be the FPGAs, maybe only the stepping level is different.

But on one board is working and on another one is not working.

I'm providing a 300ms long reset signal as requested on the V4 user guide but the DCM doesn't get locked.

The input is a 100MHz clock and the sys_clock_dcm signal is valid, but I don't get the divided, multiplied and FX clocks, and the lock signal is down.

The same bitstream is working on

SYSTEM_DCM: DCM generic map ( CLKFX_DIVIDE => 8, CLKFX_MULTIPLY => 2 ) port map ( CLKIN => adc1_clk_in, CLKFB => sys_clock_dcmfb, DSSEN => '0', PSINCDEC => '0', PSEN => '0', PSCLK => '0', RST => my_dcm_reset, CLK0 => sys_clock_dcm, CLKDV => sys_clock_x05_i, CLK2X => sys_clock_x2_i, CLKFX => sys_clock_fx_i, LOCKED => sys_lock );

sys_clock_dcm_bufg: BUFG port map( I => sys_clock_dcm, O =>

sys_clock_dcmfb);

Reply to
Nemesis
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With a sample size of just two boards, it's possible that your clock source is not within the required jitter specs to achieve lock. What is the source? Possibly an oscillator with a PLL to produce the required frequency?

Reply to
Gabor

Or maybe cascaded DCMs?

Reply to
Symon

We use a good quartz oscillator ... and just one DCM. I think I found the problem in the frequency ranges, I use the FX output to generate a

25MHz ... but on the Virtex DataSheet is written that in the Max Speed Mode, the lower limit for FX output is 32. Still I don't understand why it is working on the other boards ...
Reply to
Nemesis

Hi,

I had similar problem with locking FX outputs. I found following solution:

---------------------------------------------------------------------------=

----- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; library UNISIM; use UNISIM.VComponents.all;

entity dfs is generic ( MVAL : integer range 1 to 32:=3D 4; DVAL : integer range 1 to 32:=3D 2; CLKINPERIOD : real :=3D 10.0

-- CLKINPERIOD : integer range 2 to 1000 :=3D

10 ); port ( CLKIN : in std_logic; DFS_RESET : in std_logic; CLKFX_OUT : out std_logic; CLKFX180_OUT : out std_logic; DFS_LOCKED : out std_logic ); end dfs;

architecture rtl of dfs is

signal DRP_OUT : std_logic_vector(15 downto

0); signal DRP_RDY : std_logic; signal DRP_ADR : std_logic_vector(6 downto 0); signal DRP_EN : std_logic; signal DRP_WE : std_logic; signal RESET_FLOP : std_logic;

signal logic0 : std_logic; signal logic1 : std_logic; signal logic0_16b : std_logic_vector(15 downto

0);

begin

logic0 MVAL, CLKIN_DIVIDE_BY_2 =3D> FALSE, CLKIN_PERIOD =3D> CLKINPERIOD, CLKOUT_PHASE_SHIFT =3D> "NONE", DCM_AUTOCALIBRATION =3D> FALSE, DCM_PERFORMANCE_MODE =3D> "MAX_SPEED", DESKEW_ADJUST =3D> "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE =3D> "LOW", DLL_FREQUENCY_MODE =3D> "LOW", DUTY_CYCLE_CORRECTION =3D> TRUE, FACTORY_JF =3D> x"F0F0", PHASE_SHIFT =3D> 0, STARTUP_WAIT =3D> FALSE ) port map ( CLK0 =3D> open, CLK180 =3D> open, CLK270 =3D> open, CLK2X =3D> open, CLK2X180 =3D> open, CLK90 =3D> open, CLKDV =3D> open, CLKFX =3D> CLKFX_OUT, CLKFX180 =3D> CLKFX180_OUT, DO =3D> DRP_OUT, DRDY =3D> DRP_RDY, LOCKED =3D> open, PSDONE =3D> open, CLKFB =3D> logic0, CLKIN =3D> CLKIN, DADDR =3D> DRP_ADR, DCLK =3D> CLKIN, DEN =3D> DRP_EN, DI =3D> logic0_16b, DWE =3D> DRP_WE, PSCLK =3D> logic0, PSEN =3D> logic0, PSINCDEC =3D> logic0, RST =3D> DFS_RESET ); P0000: process(CLKIN) begin if rising_edge(CLKIN) then if (DFS_RESET =3D '1') then RESET_FLOP

Reply to
jerzy.gbur

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