I'm using the DCM instantiation reported below, on a Virtex4fx60 target. I have two different boards (ICS-8550) the differ only for the ruggedization level, the boards are almost the same and so should be the FPGAs, maybe only the stepping level is different.
But on one board is working and on another one is not working.
I'm providing a 300ms long reset signal as requested on the V4 user guide but the DCM doesn't get locked.
The input is a 100MHz clock and the sys_clock_dcm signal is valid, but I don't get the divided, multiplied and FX clocks, and the lock signal is down.
The same bitstream is working on
SYSTEM_DCM: DCM generic map ( CLKFX_DIVIDE => 8, CLKFX_MULTIPLY => 2 ) port map ( CLKIN => adc1_clk_in, CLKFB => sys_clock_dcmfb, DSSEN => '0', PSINCDEC => '0', PSEN => '0', PSCLK => '0', RST => my_dcm_reset, CLK0 => sys_clock_dcm, CLKDV => sys_clock_x05_i, CLK2X => sys_clock_x2_i, CLKFX => sys_clock_fx_i, LOCKED => sys_lock );
sys_clock_dcm_bufg: BUFG port map( I => sys_clock_dcm, O =>
sys_clock_dcmfb);