Latest threads in Field-Programmable Gate Arrays

fpga async design help me

hi I need help with my async desgin. I'm using xilinx virtex-ii. I'm very new with async stuff and so my understanding...

1 21yrs

perltcl

1 21yrs perltcl

Parallelsignal at 85 MHz

Hi, I want to build a dvi to lvds konverter. Betweeen there two busses, I have a 24 bit parallel bus. Eventually I want...

2 21yrs

benjamin

2 21yrs benjamin

RAM Synthesized away

Hi, I use an RAM Block of 28x64 words in my design (Ouartus II 4.2 SP1). I have built the RAM with the integrated MegaF...

3 21yrs

alexander.korff

3 21yrs alexander.korff

4/1

Hmmmmm, Are all of the posts today in honor of April Fools day? I am having a hard time seeing if these are serious, or...

3 21yrs

austin

3 21yrs austin

ABEL alias names

Hi, I am having trouble finding directive to call a port by different names in ABEL HDL (Xilinx). Could someone let me k...

1 21yrs

prachar

1 21yrs prachar

Transputer delivery

If anyone is still interested in Transputers, I am now releasing the 1st half of a new FPGA Transputer through email, m...

2 21yrs

johnjakson

2 21yrs johnjakson

Xilinx tools, bugs all around?

Hi is it only me that every time I try to use some a little advance feature I trap into some Xilinx bug?? 1) implementi...

5 21yrs

antti

5 21yrs antti

Searching for Vision Concavity Algorithm

I am looking for a morphology operator that will detect the concavity of binarized shapes. And, if any one is in the kn...

8 21yrs

bradsmallridge

8 21yrs bradsmallridge

problem in driving I2C bus through memory-mapped register

Hi, I have an fpga which is accessed from ARM as a memory-mapped device. A register in fpga is used to drive a I2C bus...

10 21yrs

shankar.vk

10 21yrs shankar.vk

Hierarchy in Schematic-VHDL Design

Hi, in QuartusII v4.2 SP1 I have the following problem: My top level file is a schematic file called "H_top.bdf" In thi...

1 21yrs

ALuPin

1 21yrs ALuPin

modelsim: Types do not match

Hi, I'm a beginner in VHDL. I'm trying to implement the xess-sdram controller. When I try to simulate it, I keep gettin...

3 21yrs

qwert0987

3 21yrs qwert0987

Virtex DCM phase alignment and CLK2X registering

When a DCM is locked, can I be sure that CLK0 and CLK2X are perfectly phase-aligned? (Virtex-4 DCM_BASE Unisim model se...

1 21yrs

stephane

1 21yrs stephane

EDK IPCore insertion

Hallo At al I try to implement a IPCore in my EDK Design but without attachment o any bus. My IP Core have some IOs and...

0 21yrs

digitreaco

0 21yrs digitreaco

About Xilnet and LWIP library access on board ML310!

Hello I want to use ethernet to transmit data from pc to ML310. I thin I can use Xilnet or LWIP library to establish th...

0 21yrs

fengmingxin_714

0 21yrs fengmingxin_714

IPIF user logic vs. Component insertion

Hi at all I tried to insert a Copmonent in my user logic of IPI COMPONENT asimonh PORT clk : IN std_logic; -- Clock Inp...

2 21yrs

digitreaco

2 21yrs digitreaco

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