When a DCM is locked, can I be sure that CLK0 and CLK2X are perfectly phase-aligned? (Virtex-4 DCM_BASE Unisim model seems to show this.)
Actually, I want to register a IOB signal on CLK0 and use it with an internal CLK2X clock. The problem is: how to know which is the 'good' rising edge of CLK2X ?
Can I drive the IOB register with CLK2X and enable it with the condition (CLK0='0') ? I think I don't respect the EN hold time of the register. And the compiler may shout on me for testing a clock!
Maybe a 1 bit counter that starts on LOCKED='1' has the same waveform as CLK0 and will not produce a gated clock warning?
Thanks for help, Stephane