Field-Programmable Gate Arrays

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Enable/Disable BSCAN_SPARTAN3

Hi, I am using JTAG and BSCAN_SPARTAN3 to scan register contents, but I need a way to disable and enable the BSCAN_SPAR...
1 comments posted 21yrs
posted by ann.lai
1 comments posted 21yrs posted by ann.lai

One or two DLLs for a SDRAM controller?

Hi, I have a Xess board with a Xilinx Spartan 3 (XC3S1000) on it and a SDRAM. There is of course code out there for acc...
5 comments posted 21yrs
posted by marius.vollmer
5 comments posted 21yrs posted by marius.vollmer

WTB NIOS-II kit

Hi, I wanted to buy a NIOS-2 eval kit, used or new. can anyone point me to appropriate sellers who, if selling new, are...
7 comments posted 21yrs
posted by zingafriend
7 comments posted 21yrs posted by zingafriend

Instantiate RAM in Spartan3

Hi, I need to instantiate a RAM in my Spartan3 FPGA. I need to be able to address 256 spaces, each space 8 bits, and ma...
3 comments posted 21yrs
posted by ann.lai
3 comments posted 21yrs posted by ann.lai

Bi-directional Pin Use

I am working on a memory interface where the data path in bi-directional. I have internal signals data_write and data_r...
4 comments posted 21yrs
posted by
4 comments posted 21yrs posted by

Xilinx ISE 7.1

I just got my copy of ISE 7.1 and noticed that I now have to click through both the GPL and the LGPL before installing....
1 comments posted 21yrs
posted by acetylcholinerd
1 comments posted 21yrs posted by acetylcholinerd

Out of Memory Error comes suddenly.

Hello. I am writing VHDL code to be synthesized on a Xilinx Spartan II FPGA. For the past month, I've been beating my h...
3 comments posted 21yrs
posted by andromodon
3 comments posted 21yrs posted by andromodon

Achieving required speed in Virtex-II Pro FPGA

Hi, ALL! Several months ago I did schematic based design, implementing median image filtering in Altera EP1K30TC144-2....
23 comments posted 21yrs
posted by v_mirgorodsky
23 comments posted 21yrs posted by v_mirgorodsky

Read Data from BlockRAM

I am using Virtex2pro - xc2vp30 to implement my HDL-based design. The output of my design will be stored in BlockRAM. H...
2 comments posted 21yrs
posted by aroutchelvame
2 comments posted 21yrs posted by aroutchelvame

Software Defined Radio

Hi, I am generally interested in SDR with FPGA. Does anybody know some nice projects or where to find good information...
1 comments posted 21yrs
posted by benjamin
1 comments posted 21yrs posted by benjamin

PID Controller implemented on FPGA

Hi.... I am a student of MS Systems Engineering, I have been assigned a project titled as "FPGA Based Field Controller(...
1 comments posted 21yrs
posted by engineerumair
1 comments posted 21yrs posted by engineerumair

Program flash memory XC18V01 from FPGA

HI: In my FPGA design, I have a serial port for monitoring service. The question is, how can I re-program the flash memo...
1 comments posted 21yrs
posted by aarodriguez
1 comments posted 21yrs posted by aarodriguez