Hi,
I'm a beginner in VHDL. I'm trying to implement the xess-sdram controller. When I try to simulate it, I keep getting errors from modelsim like: 'Types do not match..'. But they are the same type. I stripped it now down to nothing else than the controller and some signals in the file. But still the errors occure. Any hints?
for example:
----8 sdram_data_in, sDOut => sdram_data_out, ... );
---->8----
Error message from modelsim:
----88----
Thanks André Schieleit