Hi,
I'm a beginner in VHDL. I'm trying to implement the xess-sdram controller. When I try to simulate it, I keep getting errors from modelsim like: 'Types do not match..'. But they are the same type. I stripped it now down to nothing else than the controller and some signals in the file. But still the errors occure. Any hints?
for example:
----8 sdram_data_in, sDOut => sdram_data_out, ... );
---->8----
Error message from modelsim:
----88----
Thanks André Schieleit
André,
What are the values of DATA_WIDTH and SD_DATA_BUS_WIDTH ? What is the generic part of your component for ?
Nicolas Pinault
André Schieleit a écrit :
You have clipped too much for an answer. But it appears the messages mean that your declaration of the component sdramCntl where it is coded does not match the declaration where it is used. The messages have nothing to do with sdram_data_in/out.
thanks for your answers. after some research I eventually found out, that using both IEEE.STD_LOGIC_ARITH.ALL and IEEE.numeric_std.all was causing my problem.
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