Latest threads in Field-Programmable Gate Arrays

Which chip should I use?

Hello, I need an FPGA chip which fulfills the following constraints: -- it has at least 64 IO lines; -- it is not very...

17 21yrs

wyderskiREMOVE

17 21yrs wyderskiREMOVE

Metastability / MUX question

I'm pretty familair with the standard 2-DFF schemes for synchronization. I came across the URL below and have a questio...

7 21yrs

localhost

7 21yrs localhost

Xilinx ISE 6.3 verilog simulation problem

I'm still new in FPGA design, and learning Verilog, and the EDA tool (Xilinx ISE, ModelSim, ...) I have a problem simul...

3 21yrs

bigboytemp

3 21yrs bigboytemp

40% less SEU's! in V4: another good reason to choose Xilinx

All, Latest update on atmospheric upsets: http://tinyurl.com/c9y5l Virtex 4 memory cells are almost twice as hard to up...

13 21yrs

austin

13 21yrs austin

newbie question

Hello, I want to start learning VHDL (or VERILOG) and FPGA programming. I have ISE 6.1 and some FPGA board. Where is th...

11 21yrs

ma

11 21yrs ma

Cant link with xil_malloc() function

Hi, I'm using the EDK 7.1 for a project and I need to use a memory manager like malloc. According to Xilinx' documentat...

1 21yrs

pbs

1 21yrs pbs

Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2

I hope one of the Xilinx gurus can help me out here... I've got a design that uses multiple V2Pro parts receiving a com...

7 21yrs

johnp3+nospam

7 21yrs johnp3+nospam

Will this DCM cascade track a frequency offset clock?

Hi all, I need to generate a 20MHz clock from a 10MHz clock on a V2Pro. Plan is to use 2 DCMs: 1st DCM: 10MHz into CLKI...

3 21yrs

no

3 21yrs no

on chip termination for DVI (TMDS) possible?

Hi, I have looked a little bit into the standard. The DVI uses a LVDS, with a 50 Ohm pullup to 3,3V on each line at the...

1 21yrs

benjamin

1 21yrs benjamin

Using capacitor to slow the rise time.

I know that we can vary the drive strength of the Virtex outputs and control the rise time. This just for my understand...

17 21yrs

brijesh_xyz

17 21yrs brijesh_xyz

Parallel Cable IV opened in "Compatibility Mode"

Hi folks, this is starting to drive me nuts: I use a Xilinx Parallel Cable IV to program some big FPGAs (big as in V2P7...

7 21yrs

smd

7 21yrs smd

FPGA choice advice needed

hello all, Could someone give me an advice of the best FPGA(s) that meets following requirements: Application: PCI boar...

12 21yrs

toto

12 21yrs toto

GSPx 2005 Call for Papers

Friends I am writing on behalf of GSPx 2005 to encourage you to submit speaker abstract on DSP-related computing applic...

3 21yrs

jleineweber

3 21yrs jleineweber

Spartan-3 boards comparison

I am about to buy an fpga dev board for personal use and am not able to decide between xess XSA-200 board which costs $...

1 21yrs

zingafriend

1 21yrs zingafriend

quantization and rate control

Hi all. Does anyone have a link to any work done in FPGA for quantization and rate control? I need this for an undergra...

0 21yrs

dan.nilsen

0 21yrs dan.nilsen

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